參數(shù)資料
型號: M13S2561616A-4TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 16M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 X 875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
文件頁數(shù): 12/48頁
文件大?。?/td> 1232K
代理商: M13S2561616A-4TG
ES MT
M13S2561616A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.3 12/48
Burst Address Ordering for Burst Length
Starting
Address (A2, A1,A0)
xx0
xx1
x00
x01
x10
x11
000
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
010
2, 3, 4, 5, 6, 7, 0, 1
011
3, 4, 5, 6, 7, 0, 1, 2
100
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
110
6, 7, 0, 1, 2, 3, 4, 5
111
7, 0, 1, 2, 3, 4, 5, 6
Burst
Length
Sequential Mode
Interleave Mode
0, 1
1, 0
0, 1
1, 0
2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
4
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is
enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S2561616A also support a weak drive strength
option, intended for lighter load and/or point-to-point environments.
Mode Register Set
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum t
RP
is required to issue MRS command.
0
1
2
3
4
5
6
7
8
CO MM AN D
t
C K
Al l B a n k s
R e g Mo d e
CoAn y
t
R P
* 2
* 1
CLK
CLK
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