參數(shù)資料
型號(hào): M13S2561616A-4TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 16M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 X 875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
文件頁數(shù): 24/48頁
文件大小: 1232K
代理商: M13S2561616A-4TG
ES MT
M13S2561616A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.3 24/48
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L
BST
( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where L
BST
equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
2
3
C L K
C L K
4
5
6
7
8
CO MM AN D
t
D Q S S
DQS
DQ 's
D M
W RITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Din 0
NOP
Din 1
Din 2
Din 3
Din 4
Din 6
Din 7
Din 5
masked by DM = H
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