參數(shù)資料
型號(hào): M13S256328A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 200萬× 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 4/47頁
文件大?。?/td> 807K
代理商: M13S256328A
ES MT
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70° )
M13S256328A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 4/47
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage
V
DD
2.3
2.7
V
I/O Supply voltage
V
DDQ
2.3
2.7
V
I/O Reference voltage
V
REF
0.49*V
DDQ
0.51*V
DDQ
V
1
I/O Termination voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+ 0.15
V
DDQ
+ 0.3
V
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
Input leakage current
I
I
-5
5
μ
A
3
Output leakage current
I
OZ
-5
5
μ
A
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
I
OH
-16.8
mA
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
I
OL
+16.8
mA
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
I
OH
-9
mA
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
I
OL
+9
mA
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
.
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