參數(shù)資料
型號: M13S256328A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 200萬× 32位× 4個銀行雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 7/47頁
文件大?。?/td> 807K
代理商: M13S256328A
ES MT
M13S256328A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 7/47
AC Timing Parameter & Specifications-continued
-5
Parameter
Symbol
min
max
Unit
Half Clock Period
t
HP
t
CL
min or t
CH
min
-
ns
DQ-DQS output hold time
t
QH
t
HP
-tQHS
-
ns
Data hold skew factor
(for DQS & associated DQ
signals)
ACTIVE to PRECHARGE
command
t
QHS
-
0.5
ns
t
RAS
40
120Kns
ns
Row Cycle Time
t
RC
55
-
ns
AUTO REFRESH Row Cycle
Time
t
RFC
70
-
ns
ACTIVE to READ delay
t
RCDRD
20
-
ns
ACTIVE to WRITE delay
t
RCDWT
10
-
ns
PRECHARGE command
period
t
RP
15
-
ns
ACTIVE to READ with
AUTOPRECHARGE
command
t
RAP
15
-
ns
ACTIVE bank A to ACTIVE
bank B command
t
RRD
10
-
ns
Write recovery time
t
WR
15
-
ns
Write data in to READ
command delay
t
WTR
2
-
t
CK
Col. Address to Col. Address
delay
t
CCD
1
-
t
CK
Average periodic refresh
interval
t
REFI
-
7.8
us
Write preamble
t
WPRE
0.25
-
t
CK
Write postamble
t
WPST
0.4
0.6
t
CK
DQS read preamble
t
RPRE
0.9
1.1
t
CK
DQS read postamble
t
RPST
0.4
0.6
t
CK
Clock to DQS write preamble
setup time
t
WPRES
0
-
ns
Load Mode Register /
Extended Mode register
cycle time
t
MRD
2
-
t
CK
Exit self refresh to READ
command
t
XSRD
200
-
t
CK
Exit self refresh to
non-READ command
t
XSNR
75
-
ns
Autoprecharge write
recovery+Precharge time
t
DAL
(t
WR
/t
CK
)
+
(t
RP
/t
CK
)
-
t
CK
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