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參數(shù)資料
| 型號(hào)： | M13S256328A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 2M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| 中文描述： | 200萬× 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 11/47頁 |
| 文件大小： | 807K |
| 代理商： | M13S256328A |
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ES MT
M13S256328A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 11/47
Burst Address Ordering for Burst Length
Starting
Address (A2, A1,A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
Burst
Length
Sequential Mode
Interleave Mode
0, 1
1, 0
0, 1
1, 0
2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
4
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the
DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be
issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S256328A also support a weak drive
strength option, intended for lighter load and/or point-to-point environments.
Mode Register Set
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum t
RP
is required to issue MRS command.
0
1
2
3
4
5
6
7
8
CO MM AN D
t
C K
Al l B a n k s
R e g Mo d e
CoAn y
t
R P
* 2
* 1
CLK
CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M13S32321A | 256K x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-6BG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-5BG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S64164A-5TG | 1M x 16 Bit x 4 Banks Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M13S256328A-5BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S32321A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:256K x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S32321A_08 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:256K x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S32321A-5L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:256K x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S32321A-6L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:256K x 32 Bit x 4 Banks Double Data Rate SDRAM |
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