參數(shù)資料
型號(hào)： M13S32321A
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 256K x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 256K × 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 13/49頁(yè)
文件大?。?/td> 769K
代理商： M13S32321A
ES MT
M13S32321A
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2006
Revision : 1.0 13/49
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not
defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode
register is written by asserting low on CS , RAS , CAS ,
WE
and high on BA0 (The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A9 and BA1 in the
same cycle as CS , RAS , CAS and
WE
going low is written in the extended mode register. The mode register contents can
be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0
is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to
low for proper EMRS operation. Refer to the table for specific codes.
BA1
BA0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
1
RFU: Must be set “0”
D.I.C
RFU: Must be set “0”
D.I.C
DLL
Extended Mode Register
A6
A1
Output Driver Impedance Control
A0
DLL Enable
0
0
Normal
0
Enable
0
1
Weak
1
Disable
1
0
RFU
1
1
Matched Impedance 60
Ω
BA1
BA0
Operating Mode
0
0
MRS Cycle
0
1
EMRS Cycle
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