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參數(shù)資料
| 型號： | M1AFS250-FQN180 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 250000 GATES, PBCC180 |
| 封裝： | 0.50 MM PITCH, QFN-180 |
| 文件頁數(shù)： | 153/318頁 |
| 文件大?。?/td> | 10129K |
| 代理商： | M1AFS250-FQN180 |
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Device Architecture
2- 220
Pr el iminar y v1 .7
VAREF
Analog Reference Voltage
The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be
used by the ADC. While using the internal reference, the reference voltage is output on the VAREF
pin for use as a system reference. If a different reference voltage is required, it can be supplied by
an external source and applied to this pin. The valid range of values that can be supplied to the
ADC is 1.0 V to 3.3 V. When VAREF is internally generated by the Fusion device, a bypass capacitor
must be connected from this pin to ground. The value of the bypass capacitor should be between
3.3 F and 22 F, which is based on the needs of the individual designs. The choice of the capacitor
value has an impact on the settling time it takes the VAREF signal to reach the required
specification of 2.56 V to initiate valid conversions by the ADC. If the lower capacitor value is
chosen, the settling time required for VAREF to achieve 2.56 V will be shorter than when selecting
the larger capacitor value. The above range of capacitor values supports the accuracy specification
of the ADC, which is detailed in the datasheet. Designers choosing the smaller capacitor value will
not obtain as much margin in the accuracy as that achieved with a larger capacitor value.
Depending on the capacitor value selected in the Analog System Builder, a tool in Libero IDE, an
automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that
VAREF has achieved the 2.56 V value. Actel recommends customers use 10 F as the value of the
bypass capacitor. Designers choosing to use an external VAREF need to ensure that a stable and
clean VAREF source is supplied to the VAREF pin before initiating conversions by the ADC.
Designers should also make sure that the ADCRESET signal is deasserted before initiating valid
conversions.2
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal
levels are compatible with the I/O standard selected. Unused I/O pins are configured as inputs with
pull-up resistors.
During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC
supplies continuously powered up, when the device transitions from programming to operating
mode, the I/Os get instantly configured to the desired user configuration.
Axy
Analog Input/Output
Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad,
T = Temperature pad, V = Voltage pad) and y is the Analog Quad number (0 to 9). There is a
minimum 1 M
Ω to ground on AV, AC, and AT. This pin can be left floating when it is unused.
ATRTNx
Temperature Monitor Return
AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes
should be connected to these pins. There is one analog return pin for every two Analog Quads. The
x in the ATRTNx designator indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1 for AQ2 and
AQ3, ..., x = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETUNxy in
the software (where x and y refer to the quads that share the return signal). ATRTN is internally
connected to ground. It can be left floating when it is unused.
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to
the global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more
detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on
Refer to the "User I/O Naming Convention" section on page 2-157 for a description of naming of
global pins.
2. The ADC is functional with an external reference down to 1V, however to meet the performance
parameters highlighted in the datasheet refer to the VAREF specification in Table 3-2 on page 3-3.
相關PDF資料 |
PDF描述 |
|---|---|
| M1AFS250-FQNG180 | FPGA, 250000 GATES, PBCC180 |
| M20-1051700 | 34 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
| M20-1051800 | 36 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS250-FQN256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FQN256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FQN256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FQNG180 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 180QFN EP - Trays |
| M1AFS250-FQNG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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