參數(shù)資料
型號(hào)： M1AFS250-FQN180
元件分類： FPGA
英文描述： FPGA, 250000 GATES, PBCC180
封裝： 0.50 MM PITCH, QFN-180
文件頁(yè)數(shù)： 53/318頁(yè)
文件大?。?/td> 10129K
代理商： M1AFS250-FQN180
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Device Architecture
2- 130
Pr el iminar y v1 .7
User I/Os
Introduction
Fusion devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-65, Table 2-66, Table 2-67, and
Table 2-68 on page 2-133 show the voltages and the compatible I/O standards. I/Os provide
programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and
3.3 V PCI-X are 5 V–tolerant. See the "5 V Input Tolerance" section on page 2-143 for possible
implementations of 5 V tolerance.
All I/Os are in a known state during power-up, and any power-up sequence is allowed without
(Commercial and Industrial)" section on page 3-5 for more information. In low power standby or
sleep mode (VCC is OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, digital inputs are
tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated.
I/O Tile
The Fusion I/O tile provides a flexible, programmable structure for implementing a large number of
I/O standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to
support high-performance register inputs and outputs, with register enable if desired (Figure 2-91
on page 2-131). The registers can also be used to support the JESD-79C DDR standard within the I/O
structure (see the "Double Data Rate (DDR) Support" section on page 2-137 for more information).
As depicted in Figure 2-92 on page 2-136, all I/O registers share one CLR port. The output register
and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-136
for more information.
I/O Banks and I/O Standards Compatibility
The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090
and AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. Figure 2-105 on
page 2-158 and Figure 2-106 on page 2-158 show the bank configuration by device. The north side
of the I/O in the AFS600 and AFS1500 devices comprises two banks of Actel Pro I/Os. The Actel Pro
I/Os support a wide number of voltage-referenced I/O standards in addition to the multitude of
single-ended and differential I/O standards common throughout all Actel digital I/Os. Each I/O
voltage bank has dedicated I/O supply and ground voltages (VCCI/GNDQ for input buffers and
VCCI/GND for output buffers). Because of these dedicated supplies, only I/Os with compatible
standards can be assigned to the same I/O voltage bank. Table 2-66 and Table 2-67 on page 2-132
show the required voltage compatibility values for each of these voltages.
For more information about I/O and global assignments to I/O banks, refer to the specific pin table
Each Pro I/O bank is divided into minibanks. Any user I/O in a VREF minibank (a minibank is the
region of scope of a VREF pin) can be configured as a VREF pin (Figure 2-91 on page 2-131). Only one
VREF pin is needed to control the entire VREF minibank. The location and scope of the VREF
minibanks can be determined by the I/O name. For details, see the "User I/O Naming Convention"
Table 2-67 on page 2-132 shows the I/O standards supported by Fusion devices and the
corresponding voltage levels.
I/O standards are compatible if the following are true:
Their VCCI values are identical.
If both of the standards need a VREF, their VREF values must be identical (Pro I/O only).
相關(guān)PDF資料
PDF描述
M1AFS250-FQNG180 FPGA, 250000 GATES, PBCC180
M20-1051700 34 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET
M20-1051800 36 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET
M20-1052400 48 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET
M20-1050200 4 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET
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