Revision 13 2-27 LVDS 24 – High – 1.55 2.26 0.25 1.95 – –– – ns LVPECL 24 – High – 1.55 2.17 0.25 1.70 – –– – ns T" />
參數資料
型號: M1AGLE3000V5-FGG896I
廠商: Microsemi SoC
文件頁數: 103/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝: 27
系列: IGLOOe
邏輯元件/單元數: 75264
RAM 位總計: 516096
輸入/輸出數: 620
門數: 3000000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 896-BGA
供應商設備封裝: 896-FBGA(31x31)
IGLOOe Low Power Flash FPGAs
Revision 13
2-27
LVDS
24
High
1.55 2.26 0.25 1.95
––
ns
LVPECL
24
High
1.55 2.17 0.25 1.70
––
ns
Table 2-26 Summary of I/O Timing Characteristics—Software Default Settings (continued)
Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI (per standard)
I/O Standard
Drive
S
trength
(mA)
Eq
uivalen
tSo
ft
ware
De
fault
Drive
S
trength
Option
1 (mA)
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(ns)
t ZH
S
(ns)
Unit
s
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-49 for
connectivity. This resistor is not required during normal operation.
5. Output drive strength is below JEDEC specification.
6. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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