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參數(shù)資料
| 型號(hào)： | M1AGLE3000V5-FGG896I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 156/166頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 896-FBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | IGLOOe |
| 邏輯元件/單元數(shù)： | 75264 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 620 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 896-BGA |
| 供應(yīng)商設(shè)備封裝： | 896-FBGA（31x31） |
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IGLOOe Low Power Flash FPGAs
Revision 13
1-3
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, Flash-based IGLOOe devices allow all functionality to be Instant On; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-
standard AES algorithm. The IGLOOe family device architecture mitigates the need for ASIC migration at
higher user volumes. This makes the IGLOOe family a cost-effective ASIC replacement solution,
especially for applications in the consumer, networking/communications, computing, and avionics
markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-based
FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot be altered
by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user
data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The
IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on page 4):
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the IGLOOe core tile as either a three-input lookup table (LUT)
equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Microsemi ProASIC family of third-generation-architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AGLE3000V5-FGG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| M1ARM 24-240VAC/DC 60MINS | 制造商:BROYCE CONTROL 功能描述:TIMER DUAL FUNCTION 60MINS 制造商:BROYCE CONTROL 功能描述:TIMER, DUAL FUNCTION, 60MINS 制造商:BROYCE CONTROL 功能描述:TIMER, DUAL FUNCTION, 60MINS, Contact Configuration:SPDT, Time Min:2min, Time Ma 制造商:BROYCE CONTROL 功能描述:TIMER, DUAL FUNCTION, 60MINS, Contact Configuration:SPDT, Time Min:2min, Time Max:60min, Timing Adjustment:Knob, Relay Mounting:DIN Rail, Contact Current AC Max:8A, Contact Current DC Max:8A, Contact Voltage AC Max:250V, Contact , RoHS Compliant: Yes |
| M1AXA-1036J | 功能描述:IDC CABLE - MSC10A/MC10G/X RoHS:是 類別:電纜組件 >> 矩形 系列:- 產(chǎn)品目錄繪圖:H1(A,B,C,D)X Series 特色產(chǎn)品:IDC Connectors and Cables 標(biāo)準(zhǔn)包裝:1 系列:- 連接器類型:插口至線纜 位置數(shù):24 行數(shù):2 間距 - 連接器:0.100"（2.54mm） 間距 - 線纜:0.050"（1.27mm） 長度:3.00'（914.40mm） 特點(diǎn):帶電極標(biāo)記，應(yīng)力釋除 顏色:多色，帶狀 屏蔽:無屏蔽 使用:- 電纜端接:IDC 觸點(diǎn)表面涂層:錫 觸點(diǎn)涂層厚度:- 產(chǎn)品目錄頁面:47 (CN2011-ZH PDF) 其它名稱:H3DXS-2436MH3DXS-2436M-ND |
| M1AXA-1036R | 功能描述:IDC CABLE - MSC10A/MC10M/X RoHS:是 類別:電纜組件 >> 矩形 系列:- 產(chǎn)品目錄繪圖:C3(A,B,C,D)E Series 標(biāo)準(zhǔn)包裝:1 系列:- 連接器類型:插口至卡邊 位置數(shù):20 行數(shù):2 間距 - 連接器:0.100"（2.54mm） 間距 - 線纜:0.050"（1.27mm） 長度:0.500'（152.40mm，6.00"） 特點(diǎn):應(yīng)力消除 顏色:多色，帶狀 屏蔽:無屏蔽 使用:- 電纜端接:IDC 觸點(diǎn)表面涂層:錫 觸點(diǎn)涂層厚度:100µin（2.54µm） 產(chǎn)品目錄頁面:36 (CN2011-ZH PDF) 其它名稱:C3BES-2006M |
| M1AXA-1040K | 功能描述:IDC CABLE - MSC10A/MC10F/X RoHS:是 類別:電纜組件 >> 矩形 系列:- 產(chǎn)品目錄繪圖:H1(A,B,C,D)X Series 特色產(chǎn)品:IDC Connectors and Cables 標(biāo)準(zhǔn)包裝:1 系列:- 連接器類型:插口至線纜 位置數(shù):24 行數(shù):2 間距 - 連接器:0.100"（2.54mm） 間距 - 線纜:0.050"（1.27mm） 長度:3.00'（914.40mm） 特點(diǎn):帶電極標(biāo)記，應(yīng)力釋除 顏色:多色，帶狀 屏蔽:無屏蔽 使用:- 電纜端接:IDC 觸點(diǎn)表面涂層:錫 觸點(diǎn)涂層厚度:- 產(chǎn)品目錄頁面:47 (CN2011-ZH PDF) 其它名稱:H3DXS-2436MH3DXS-2436M-ND |
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