5-6 Revision 13 Revision 3 (cont’d) Table 2-14 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings" />
參數(shù)資料
型號(hào)： M1AGLE3000V5-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 71/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標(biāo)準(zhǔn)包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計(jì)： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
Datasheet Information
5-6
Revision 13
Revision 3 (cont’d)
Settings1 was updated to change PDC3 to PDC7. The table notes were updated
to reflect that power was measured on VCCI. Table note 4 is new.
Static Power Consumption in IGLOO Devices were updated to add PDC6 and
PDC7, and to change the definition for PDC5 to bank quiescent power.
calculation of PSTAT, including PDC6 and PDC7.
Footnote 1 was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to
PPLL = PDC4 + PAC13 * FCLKOUT.
The "Timing Model" was updated to be consistent with the revised timing
numbers.
changed to TA in notes 1 and 2.
to included a hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
Revision 2 (Jun 2008)
Product Brief v1.0
The product brief section of the datasheet was divided into two sections and
given a version number, starting at v1.0. The first section of the document
includes features, benefits, ordering information, and temperature and speed
grade offerings. The second section is a device family overview.
N/A
Revision 2 (cont’d)
Packaging v1.1
The naming conventions changed for the following pins in the "FG484" for the
A3GLE600:
Pin Number
New Function Name
J19
IO45PPB2V1
K20
IO45NPB2V1
M2
IO114NPB6V1
N1
IO114PPB6V1
N4
GFC2/IO115PPB6V1
P3
IO115NPB6V1
Revision 1 (Mar 2008)
Product Brief rev. 1
The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 W)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the "Pro (Professional) I/O"
Revision 0 (Jan 2008) This document was previously in datasheet Advance v0.4. As a result of moving
to the handbook format, Actel has restarted the version numbers. The new
version number is 51700096-001-0.
N/A
Revision
Changes
Page
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