Revision 13 3-5 TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal w" />
參數(shù)資料
型號： M1AGLE3000V5-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 34/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應商設備封裝： 896-FBGA（31x31）
IGLOOe Low Power Flash FPGAs
Revision 13
3-5
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The
values in Table 3-2 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500
to 1 k will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Table 3-3 TRST and TCK Pull-Down Recommendations
VJTAG
Tie-Off Resistance*
VJTAG at 3.3 V
200
to 1 k
VJTAG at 2.5 V
200
to 1 k
VJTAG at 1.8 V
500
to 1 k
VJTAG at 1.5 V
500
to 1 k
Note: Equivalent parallel resistance if more than one device is on the JTAG chain
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