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Page 54
8. Clock Generating Circuit
p
u
o
r
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8
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6
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Figure 8.7 Clock transition
Wait mode
CPU operation stopped
CM10=“1”
Transition of stop mode, wait mode
BCLK :f(XIN)/8
CM07=“0” MCD=“0816”
Main clock is oscillating
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: When shifting to division by 8 mode, MCD is set to "0816".
Main clock is oscillating
Sub clock is stopped
CM04=“1”
MCD=“XX16”
Note 1, 3
CM04=“0”
BCLK :f(XIN)
/division rate
CM07=“0” MCD=“XX16”
Note 4
BCLK :f(XIN)
CM07=“0” MCD=“1216”
High-speed mode
Medium-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
BCLK :f(XIN)
/division rate
CM07=“0” MCD=“XX16”
Note 4
BCLK :f(XIN)
CM07=“0” MCD=“1216”
High-speed mode
Medium-speed mode
(divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode)
Medium-speed mode (divided-by-8 mode)
Transition of normal mode
Normal mode
CM10=“1”
Stop mode
All oscillators stopped
Wait mode
CPU operation stopped
CM04=“1”
CM05=“0”
Note 4
BCLK :f(XCIN)
CM07=“1”
Low-speed mode
BCLK :f(XCIN)
CM07=“1”
Main clock is oscillating
Sub clock is oscillating
MCD=“XX16”
Note 1, 3
CM07=“0
Note 1
MCD=“XX16”
Note 3
CM07=“1”
Note 2
CM10=“1”
Stop mode
All oscillators stopped
Wait mode
CPU operation stopped
(Please see the following as transition of normal mode.)
CM07=“0”
Note 1
MCD=“XX16”
Note 3
CM04=“1”
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
Low power
dissipation mode
CM05=“1”
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Medium-speed mode
(Divided-by-8 mode)
Note 1
Note 2
Note 1
Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped,
transferred to the middle speed mode.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: The main ckock devision register is set to the division by 8 mode (MCD="0816").
Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="0816").
Please change according to a direction of an arrow.
High-speed/medium-speed mode
Low-speed/low power dissipation mode
Main clock is stopped
Sub clock is oscillating
Reset
Note 4
Note 3