Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Interrupts
84
(5) INT instruction interrupt
This interrupt occurs when the INT instruction is executed after specifying a software interrupt number
from 0 to 63. Note that software interrupt numbers 7 to 54 and 57 are assigned to peripheral I/O
interrupts. This means that by executing the INT instruction, you can execute the same interrupt
routine as used in peripheral I/O interrupts.
The stack pointer used in INT instruction interrupt varies depending on the software interrupt number.
For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The
previous U flag before the interrupt occurred is restored when control returns from the interrupt rou-
tine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur.
However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose ISP.
Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software
interrupt number 32 to 54 and 57.
Hardware Interrupts
There are Two types of hardware Interrupts; special interrupts and Peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
Reset
____________
A reset occurs when the RESET pin is pulled low.
______
NMI interrupt
______
This interrupt occurs when the NMI pin is pulled low.
Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
Ocsillation stop detect interrupt
This interrupt is caused by the ocsillation stop detect function.
It occurs when detecting the XIN ocsillation is stopped.
Single-step interrupt
This interrupt is used exclusively for debugger purposes. These interrupts normally do not need to use
this interrupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is
generated each time an instruction is executed.
Address-match interrupt
This interrupt occurs when the program's execution address matches the contents of the address
match register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.