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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片32位CMOS微機(jī) |
| 文件頁數(shù)： | 8/45頁 |
| 文件大?。?/td> | 565K |
| 代理商： | M32000D3FP |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
8
type
bus
control
(cont.)
pin name
DC*
name
data complete
I/O
I/O
(Hi-z)
function
When the M32000D3FP drives an external bus cycle, it
automatically inserts wait cycles until DC is input by the slave
device in the system bus.
When the M32000D3FP is in the hold state and the internal
DRAM is accessed from an external bus master, the M32000D3FP
__
outputs DC to notify to the external bus master that the bus
cycle to the internal DRAM has been completed.
Bus right request input pin of the system bus. When HREQ is an
"L" level, the M32000D3FP switches to the hold state.
Indicates that the M32000D3FP has switched to the hold state
and releases the bus right of the system bus to the requestor.
Signal input to the M32000D3FP when it is in the hold state to
request access to the internal DRAM from an external bus master.
__
When an "L" level is input to CS, the M32000D3FP accesses the
internal DRAM at the address input via the address pins.
System break interrupt input pin. The SBI is not masked by the
IE bit in the PSW register. It is also used to return from CPU
sleep mode and to request the start of operation in slave mode.
External interrupt request input pin. It is also used to return from
CPU sleep mode and to request the start of operation the slave
mode.
Two programmable I/O ports.
______
hold
input
HACK
hold
acknowledge
chip
select
output
__
CS
input
interrupt
controller
___
SBI
system
break
interrupt
external
interrupt
input
INT
input
programm-
able I/O port
* The DC pin becomes an output pin when the CS signal is input to the M32000D3FP.
PP0, PP1
port
I/O
PIN DESCRIPTION (3/3)
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| M32002AGMJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
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