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| 型號(hào)： | M34501E4FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機(jī)的CMOS |
| 文件頁數(shù)： | 103/113頁 |
| 文件大小： | 1252K |
| 代理商： | M34501E4FP |
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103
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
RECOMMENDED OPERATING CONDITIONS 1
(Ta = –20 °C to 85 °C, V
DD
= 2.7 to 5.5 V, unless otherwise noted)
Symbol
V
DD
V
RAM
V
SS
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
I
OL
(peak)
I
OL
(peak)
I
OL
(peak)
I
OL
(peak)
I
OL
(avg)
I
OL
(avg)
I
OL
(avg)
I
OL
(avg)
Σ
I
OL
(avg)
Parameter
Supply voltage
RAM back-up voltage
Supply voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level total average current
Notes 1: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less.
2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (system enters into the reset state when the value is
VRST or less). In the RAM back-up mode with the POF2 instruction, the voltage drop detection circuit stops.
3: The average output current (I
OH
, I
OL
) is the average value during 100 ms.
Unit
Conditions
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
(at RAM back-up mode with the POF2
instruction)
P0, P1, P2, D
2
, D
3
, X
IN
D
0
, D
1
RESET
C, K
CNTR, INT
P0, P1, P2, D
0
–D
3
, X
IN
C, K
RESET
CNTR, INT
P2,
RESET
D
0
, D
1
D
2
/C, D
3
/K
P0, P1
P2,
RESET
(Note 3)
D
0
, D
1
(Note 3)
D
2
/C, D
3
/K (Note 3)
P0, P1 (Note 3)
P2, D,
RESET
P0, P1
Max.
5.5
V
DD
12
V
DD
V
DD
V
DD
V
DD
0.2V
DD
0.16V
DD
0.3V
DD
0.15V
DD
10
40
24
24
5.0
30
15
12
80
80
Limits
Typ.
Min.
2.7
(Note 1)
1.8 (Note 2)
0.8V
DD
0.8V
DD
0.85V
DD
0.5V
DD
0.7V
DD
0.85V
DD
0
0
0
0
0
f(X
IN
)
≤
4.4 MHz
V
DD
= 4.0 to 5.5 V
V
DD
= 2.7 to 5.5 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
DD
= 5.0 V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
4.4
f [MHz]
f [MHz]
Ceramic resonator and high-speed mode selected
External clock input (ceramic resonator selected)
Recommended operating
condition
4.2
2.7
5.5
V
DD
[V]
V
RST
(Note)
3.2
4.2
2.7
5.5
V
DD
[V]
V
RST
(Note)
Recommended operating
condition
It shows the electrical characteristics range of detected voltage
for voltage drop detection circuit.
System reset occurs when the supply voltage is under
the detected voltage for voltage drop detection circuit.
Note:
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