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參數(shù)資料
| 型號： | M34501E4FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機的CMOS |
| 文件頁數(shù)： | 23/113頁 |
| 文件大?。?/td> | 1252K |
| 代理商： | M34501E4FP |
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23
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(3) Notes on interrupts
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
Depending on the input state of the P1
3
/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to
“
0
”
(refer to Figure 18
)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
after executing at least one instruction (refer to Figure 18
).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18
).
LA
TV1A
LA
TI1A
NOP
SNZ0
4
; (
0
2
)
; The SNZ0 instruction is valid...........
; (1
2
)
; Control of INT pin input is changed
...........................................................
; The SNZ0 instruction is executed
(EXF0 flag cleared)
...........................................................
8
NOP
: these bits are not used here.
Fig. 18 External 0 interrupt program example-1
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the RAM back-up mode is
selected and the input of INT pin is disabled, be careful about the
following notes.
When the key-on wakeup function of port P1
3
is not used (regis-
ter K1
3
=
“
0
”
), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 19
).
LA
TI1A
DI
EPOF
POF
0
; (00
2
)
; Input of INT disabled........................
; RAM back-up
: these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P1
3
/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
Depending on the input state of the P1
3
/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to
“
0
”
(refer to Figure 20
)
and then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
after executing at least one instruction (refer to Figure 20
).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20
).
LA
TV1A
LA
TI1A
NOP
SNZ0
4
; (
0
2
)
; The SNZ0 instruction is valid...........
12
; Interrupt valid waveform is changed
...........................................................
; The SNZ0 instruction is executed
(EXF0 flag cleared)
...........................................................
NOP
: these bits are not used here.
Fig. 20 External 0 interrupt program example-3
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