3
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
ROM
Function
111
0.68
μ
s (at 4.4 MHz oscillation frequency, in high-speed mode)
2048 words
10 bits
4096 words
10 bits
128 words
4 bits
256 words
4 bits
Four independent I/O ports.
Input is examined by skip decision.
Ports D
2
and D
3
are equipped with a pull-up function and a key-on wakeup function. Both func-
tions can be switched by software.
Ports D
2
and D
3
are also used as ports C and K, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P1
2
and P1
3
are also used as CNTR and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
1-bit I/O; Port C is also used as port D
2
.
1-bit I/O; Port K is also used as port D
3
.
1-bit I/O; CNTR pin is also used as port P1
2
.
1-bit input; INT pin is also used as port P1
3
.
Two independent I/O ports. A
IN0
–
A
IN1
is also used as ports P2
0
, P2
1
, respectively.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has a event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 channel (A
IN0
pin, A
IN1
pin)
4 (one for external, two for timer, one for A-D)
1 level
8 levels
CMOS silicon gate
20-pin plastic molded SOP (20P2N-A)
–
20
°
C to 85
°
C
VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage
drop detection circuit characteristics.)
1.7 mA (at V
DD
= 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)
0.1
μ
A (at room temperature, V
DD
= 5 V, output transistors in the cut-off state)
Input/Output
ports
M34501M2
M34501M4/E4
M34501M2
M34501M4/E4
I/O
I/O
I/O
I/O
I/O
I/O
Timer I/O
Interrupt input
Analog input
Timers
A-D converter
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)
RAM
D
0
–
D
3
P0
0
–
P0
3
P1
0
–
P1
3
P2
0
, P2
1
C
K
CNTR
INT
A
IN0
, A
IN1
Timer 1
Timer 2
Analog input
Sources
Nesting
Active mode
RAM back-up mode