參數(shù)資料
型號(hào): M34501E4FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù): 25/113頁(yè)
文件大?。?/td> 1252K
代理商: M34501E4FP
25
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 22 Timers structure
1
6
-
b
i
t
t
i
m
e
r
(
W
D
T
)
1
16
I
n
s
t
r
u
c
t
i
o
n
c
l
o
c
k
Q
S
Q
2
T
D
W
D
R
F
ORCLK
X
I
N
1
/
4
1
/
1
6
W
1
3
0
1
0
1
W
1
2
D
i
v
i
s
i
o
n
c
i
r
c
u
i
t
d
i
v
i
d
e
d
b
y
8
d
i
v
i
d
e
d
b
y
4
d
i
v
i
d
e
d
b
y
2
P
1
2
/
C
N
T
R
P1
2
output
0
1
W6
0
0
1
W2
3
(TR1AB)
T
1
F
T2F
(TAB1)
0
1
W
1
1
W
0
2
1
,
0
W
2
0
1
1
10
01
1
/
2
0
1
W6
1
1
/
2
(T2AB)
(TAB2)
(TAB1)
(TAB2)
(
N
o
t
e
2
)
(
N
o
t
e
2
)
T1AB
T1AB
MR
3
, MR
2
1
1
0
0
0
1
10
W
1
0
0
1
Q
R
S
0
1
2
0
1
I1
1
P
1
3
/
I
N
T
(N
o
t
e
1
)
I1
0
W
n
2
2
a
T
i
m
e
r
1
u
n
d
e
r
f
l
o
w
s
i
g
l
I1
3
Q
R
S
W
E
F
Reset signal
D
W
D
T
i
n
+
n
o
s
t
r
u
c
t
i
o
n
W
R
S
T
(
N
i
s
e
t
r
4
u
)
c
t
i
o
n
t
R
W
D
F
1
WRST instruction
(Note 3)
T
i
m
e
r
1
(
8
)
T
i
n
i
m
t
e
e
r
r
u
1
p
t
r
Reload register R1 (8)
Register B R
e
g
i
s
t
e
r
A
Timer 2 (8)
Reload register R2 (8)
Register B Register A
Timer 2
interrupt
D
r
e
(
a
a
t
a
i
s
t
o
t
-
i
e
r
s
r
e
s
l
e
w
o
t
h
a
a
e
d
u
n
f
t
u
o
t
i
n
m
m
c
a
e
t
i
t
i
c
1
n
a
o
)
l
l
r
y
2
f
r
o
u
m
n
e
e
a
r
f
c
l
o
h
w
r
s
e
l
o
a
d
g
u
r
o
d
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P1
3
/INT pin selected by
bits 1 (I1
1
) and 2 (I1
2
) of register I1.
2: Count source is stopped by clearing to
0.
3: When the WRST instruction is executed at
WDF1 flag =
1,
WDF1 flag is cleared to
0
and the next instruction is skipped.
When the WRST instruction is executed at
WDF1 flag =
0,
skip is not executed.
4: When the DWDT and WRST instructions are
executed continuously, WEF flag is cleared to
0
and reset by watchdog timer is not executed.
Instruction clock
Internal clock
generating circuit
(divided by 3)
P
r
e
s
c
a
l
e
r
One-sided edge
detection circuit
B
d
o
e
t
t
h
e
c
e
t
d
i
o
g
n
e
s
c
r
i
c
u
i
t
FI1
Rising
C
g
c
l
o
n
r
c
c
e
u
k
r
i
a
t
e
i
t
i
o
n
S
y
s
t
e
m
c
l
o
c
k
Timer 1 underflow signal
Timer 2 underflow signal
Reset signal
W
r
e
a
s
t
e
c
t
h
s
d
i
o
g
g
n
a
l
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