參數(shù)資料
型號(hào): M36DR432A100ZA6C
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,雙行,頁(yè)閃存和4兆位256K x16的SRAM,多個(gè)存儲(chǔ)產(chǎn)品
文件頁(yè)數(shù): 33/52頁(yè)
文件大?。?/td> 834K
代理商: M36DR432A100ZA6C
33/52
M36DR432AD, M36DR432BD
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
Note: Addresses are latched on the falling edge of EF, Data is latched on the rising edge of EF.
Table 20. Flash Write AC Characteristics, Chip Enable Controlled
Note: 1. To be characterized
Symbol
Alt
Parameter
M36DR432AD, M36DR432BD
Unit
85
100
120
Min
Max
Min
Max
Min
Max
t
AVAV
t
WC
Address Valid to Next Address Valid
85
(1)
100
120
ns
t
WLEL
t
WS
Write Enable Low to Chip Enable Low
0
0
0
ns
t
ELEH
t
CP
Chip Enable Low to Chip Enable High
50
(1)
50
50
ns
t
DVEH
t
DS
Input Valid to Chip Enable High
40
(1)
50
50
ns
t
EHDX
t
DH
Chip Enable High to Input Transition
0
0
0
ns
t
EHWH
t
WH
Chip Enable High to Write Enable High
0
0
0
ns
t
EHEL
t
CPH
Chip Enable High to Chip Enable Low
30
30
30
ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
0
0
0
ns
t
ELAX
t
AH
Chip Enable Low to Address Transition
50
50
50
ns
t
GHEL
Output Enable High Chip Enable Low
0
0
0
ns
t
VDHWL
t
VCS
V
DD
High to Write Enable Low
50
50
50
μs
t
EHGL
t
OEH
Chip Enable High to Output Enable Low
30
30
30
ns
t
PLQ7V
RPF Low to Reset Complete During
Program/Erase
15
15
15
μs
AI07315
EF
GF
WF
A0-A20
DQ0-DQ15
VALID
VALID
VDDF
tVDHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEH
tGHEL
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M36DR432DA85ZA6T 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
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M36DR432CZA 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
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