參數(shù)資料
型號(hào): M36DR432DA85ZA6T
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,雙行,頁閃存和4兆位256K x16的SRAM,多個(gè)存儲(chǔ)產(chǎn)品
文件頁數(shù): 1/52頁
文件大?。?/td> 834K
代理商: M36DR432DA85ZA6T
1/52
February 2003
M36DR432AD
M36DR432BD
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
I
Multiple Memory Product
– 1 bank of 32 Mbit (2Mb x16) Flash Memory
– 1 bank of 4 Mbit (256Kb x16) SRAM
I
SUPPLY VOLTAGE
– V
DDF
= V
DDS
=1.65V to 2.2V
– V
PPF
= 12V for Fast Program (optional)
I
ACCESS TIMES: 85ns, 100ns, 120ns
I
LOW POWER CONSUMPTION
I
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code, M36DR432AD: 00A0h
– Bottom Device Code, M36DR432BD: 00A1h
FLASH MEMORY
I
MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit, 28 Mbit
– Parameter Blocks (Top or Bottom location)
I
PROGRAMMING TIME
– 10μs by Word typical
– Double Word Program Option
I
ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 Words
– Page Access: 35ns
– Random Access: 85ns, 100ns, 120ns
I
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
I
BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
I
COMMON FLASH INTERFACE (CFI)
– 64 bit Unique Device Identifier
– 64 bit User Programmable OTP Cells
Figure 1. Package
I
ERASE SUSPEND and RESUME MODES
I
100,000 PROGRAM/ERASE CYCLES per
BLOCK
I
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
SRAM
I
4 Mbit (256Kb x16)
I
LOW V
DDS
DATA RETENTION: 1.0V
I
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
FBGA
Stacked LFBGA66 (ZA)
12 x8mm
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