100
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0”, unless otherwise noted)
Memory expansion and Microprocessor mode : High-speed running
Symbol
Parameter
Unit
tw(
φH), tw(φL)
td(
φ1–WR)
td(
φ1–RD)
__
tw(WR)
__
tw(RD)
td(A–WR)
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
td(WR–DLQ/DHQ)
tpxz(WR–DLZ/DHZ)
td(ALE–WR)
td(ALE–RD)
tw(ALE)
th(WR–A)
th(RD–A)
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
th(WR–DLQ/DHQ)
tpzx(WR–DLZ/DHZ)
td(LA–WR)
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tPXZ(RD–DLZ)
tPZX(RD–DLZ)
td(WR–PiQ)
φ high-level pulse width, φ low-level pulse width
___
WR output delay time
___
RD output delay time
___
WR low-level pulse width
___
RD low-level pulse width
Address output delay time
____
BHE output delay time
____
BHE output delay time
____
BHE output delay time
Chip select output delay time
Data output delay time
Floating start delay time
ALE output delay time
ALE pulse width
Address hold time
____
BHE hold time
____
BHE hold time
Chip select hold time
Data hold time
Floating release delay time
Address output delay time
Address hold time
Floating start delay time
Floating release delay time
Port Pi data output delay time (i = 4—9, 11)
Min.
5
–7
55
25
10
25
10
25
10
4
10
15
0
15
5
10
15
3-
φ access
Max.
12
35
30
5
60
4
φ access
Min.
5
–7
80
45
35
45
35
45
35
4
35
10
15
0
40
30
10
15
Max.
12
35
30
5
60
Min.
5
–7
130
45
35
45
35
45
35
4
35
10
15
0
40
30
10
15
5-
φ access
Max.
12
35
30
5
60
ns
(Note)
: f(XIN) = 20 MHz when the clock source selet bit = “1”
Note: Since the values depend on external clock frequency f(XIN), calculate them by using the bus timing data formulas on the next page.