參數(shù)資料
型號： M37754S4CHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 45/115頁
文件大小： 1571K
代理商： M37754S4CHP
34
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 37 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, bit 0 in the timer
Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
flag is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bits 2, and 3
are “0” and at the rise of the input signal when bit 3 is “0” and bit 2 is
“1”.
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the same
way as for timer mode.
(3) Pulse period measurement/pulse width
measurement mode [10]
Figure 38 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement mode.
In pulse period measurement/pulse width measurement mode, bit 0
must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select the
clock source. The selected clock is counted when the count start flag
is “1” and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”. In
pulse period measurement mode, the selected clock is counted dur-
ing the interval starting at the fall of the input signal from the TBiIN pin
to the next fall or at the rise of the input signal to the next rise; the
result is stored in the reload register. In this case, the reload register
acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input signal
to the next fall. When bit 2 is “1“, the clock is counted from the rise of
the input signal to the next rise.
In the case of counting from the fall of the input signal to the next fall,
counting is performed as follows. As shown in Figure 39, when the
fall of the input signal from TBiIN pin is detected, the contents of the
counter is transferred to the reload register. Next the counter is
cleared and count is started from the next clock. When the fall of the
next input signal is detected, the contents of the counter is trans-
ferred to the reload register once more, the counter is cleared, and
the count is started. The period from the fall of the input signal to the
next fall is measured in this way.
After the contents of the counter is transferred to the reload register,
an interrupt request signal is generated and the interrupt request bit
in the timer Bi interrupt control register is set. However, no interrupt
request signal is generated when the contents of the counter is trans-
ferred first to the reload register after the count start bit is set to “1”.
When bit 3 is “1”, the pulse width measurement mode is selected.
Pulse width measurement mode is the same as the pulse period
measurement mode except that the clock is counted from the fall of
the TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 40.
Fig. 36 Timer Bi mode register bit configuration during timer mode
Fig. 37
Timer Bi mode register bit configuration during event
counter mode
Fig. 38 Timer Bi mode register bit configuration during pulse period
measurement/pulse width measurement mode
0 0 : Always “00” in timer mode
× × : Not used in timer mode and
may be any
Not used in timer mode
Clock source select bit
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
76543210
0
×
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of
input signal
0 1 : Count at the rising edge of
input signal
1 0 : Count at the both falling edge
and rising edge of input signal
× × × : Not used in event counter mode
76543210
1
0
×
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of
input signal to the next rising one
and from the rising edge to the
next falling one
Timer Bi overflow flag
Clock source select bit
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
76543210
0
1
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
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