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參數(shù)資料
| 型號(hào)： | M37754S4CHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 60/115頁(yè) |
| 文件大?。?/td> | 1571K |
| 代理商： | M37754S4CHP |
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
48
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 59 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
Bit 0 of the UARTj Transmit/Receive mode register and UARTk
Transmit/Receive mode register must be set to “1” and bits 1 and 2
must be “0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj Transmit/Receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk Transmit/Receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (TCS0) and bit 1 (TCS1) of the
clock-sending-side UARTj Transmit/Receive control register 0. As
shown in Figure 54, the selected clock is divided by (n+1), then by 2,
is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is Pfi,
Bit Rate = Pfi/ {(n+1)
×2}
On the clock receiving side, the TCS0 and TCS1 bits of the UARTk
Transmit/Receive control register 0 are ignored because an external
clock is selected.
Bit 2 of the clock-sending-side UARTj Transmit/Receive control reg-
____
ister 0 is cleared to “0” to select CTSj input. Bit 2 of the clock receiv-
____
ing side is set to “1” to select RTSk output.
Bit 4 of the UART Transmit/Receive control register 0 is used to de-
____
termine whether to use CTS or RTS signal. Bit 4 must be “0” when
____
CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig-
____
nals are not used. When CTS and RTS signals are not used, CTS/
____
RTS pin can be used as a normal port. The case using CTS and RTS
____
signals are explained below. However, when CTS and RTS signals
____
are not used, there are no condition of CTSj input, and there is no
_____
RTSk output.
Fig. 59 Clock synchronous serial communication
UARTj transmit register
TxDj
RxDj
CLKj
CTSj
UARTj transmit buffer register
UARTj receive buffer register
UARTj receive register
UARTj Transmit/Receive mode register
UARTj Transmit/Receive control
register 0
UARTj Transmit/Receive control
register 1
0
××
×
00
0
TX
EPTY
MSB/
LSB
TCS1 TCS0
RE
RI
OER
FER
PER
SUM
TI
TE
0
UARTk transmit register
UARTk transmit buffer register
UARTk receive buffer register
UARTk receive register
UARTk Transmit/Receive mode register
UARTk Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 1
0
××
×
××
11
0
1
TX
EPTY
MSB/
LSB
RE
RI
OER
FER
PER
SUM
TI
TE
0
1
TxDk
RxDk
CLKk
RTSk
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