參數(shù)資料
型號： M37754S4CHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 84/115頁
文件大?。?/td> 1571K
代理商： M37754S4CHP
69
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby
state.
Table 7 shows the relation between standby state and each block’s
operation.
The WIT/STP state is terminated by interrupt acceptance or reset.
Accordingly, it is necessary to prepare the state in which any inter-
rupt can be accepted before the WIT/STP instruction is executed.
WIT instruction
When the WIT instruction is executed with the internal clock stop
select bit at WIT (bit 2 of particular function select register 1; Figure
62) = “0”, the clock sources
φ BIU and φ CPU are stopped at “L”, how-
ever, the oscillation circuit, the clock source
φ 1, and the divided
clocks Pf2 to Pf512, Wf32, Wf512 are not stopped. Accordingly, al-
though the CPU and bus interface unit stop operation, internal pe-
ripheral devices which use these divided clocks can operate even at
WIT state.
Otherwise, when the WIT instruction is executed with the internal
clock stop select bit at WIT = “1”, the oscillation circuit is not stopped,
however, the clock source
φ 1, divided clocks, and the clock sources
φ BIU and φ CPU are stopped. Accordingly, in this case, all of the inter-
nal peripheral devices and the watchdog timer which use divided
clocks Pf2 to Pf512, Wf32, and Wf512 are stopped.
When internal peripheral devices are not used in WIT state, the lat-
ter state (internal clock stop select bit at WIT = “1”) is more effective
to reduce current consumption.
Make sure to set the internal clock stop select bit at WIT to “1” imme-
diately before the WIT instruction execution and clear the bit to “0”
immediately after the WIT state is terminated.
The WIT state is terminated when an interrupt request is accepted,
and the internal clock
φ operation is restarted. Interrupt processing
can immediately be executed because oscillation circuit’s operation
is not stopped during WIT state.
STP instruction
When the STP instruction is executed, the oscillation circuit is
stopped and the clock sources
φ 1, φ BIU and φ CPU are at “L”. Fur-
thermore, “FFF16” is automatically set into the watchdog timer, and
its clock source is forced to connect with Wf32 when the watchdog
timer clock select bit = “0”, or Pf32 when the bit = “1”. This connection
is cut off when the most significant bit of the watchdog timer be-
comes “0” or the microcomputer is reset, and the clock source is con-
nected with the input depending on the contents of the watchdog
timer frequency select register and the watchdog timer clock select
bit. In STP state, all of the internal peripheral devices and the watch-
dog timer which use divided clocks Pf2 to Pf512, Wf32, and Wf512 are
stopped.
The STP state is terminated by reset or interrupt request accep-
tance, and then oscillation is restarted. At the same time, supply of
the clock source
φ 1 and divided clocks Pf2 to Pf512, Wf32 and Wf512
is restarted.
In that condition, when the STP return select bit (bit 7 of particular
function select register 0) is “0”, the clock sources
φ BIU and φ CPU
stop at “L” until the most significant bit of the watchdog timer
decremented with divided clock Pf32 or Wf32 becomes “0”. However,
supply of the clock sources
φ BIU and φ CPU is restarted immediately
after the oscillation restarts by reset. Accordingly, in this case, wait
for enough time to stabilize the oscillation before the reset input of
“H”.
Otherwise in that condition, when the STP return select bit is “1”,
supply of the clock sources
φ BIU and φ CPU is restarted at the timing
of the divided clock Pf16’s “H” to “L” after the oscillation restarts. This
function makes it possible to immediately return from STP state
when the clock supply input to the XIN from the external is stabilized.
Even though clocks are input from the external, make sure to clear
the STP return select bit to “0” if the external clock is unstable for a
short time when returning from STP state
Instruction
Internal clock
stop bit at WIT
Oscillation
circuit
φ 1
Operating
Stopped
(“L”)
Stopped
(“L”)
Pf2 to Pf512
Operating
Stopped
(“H”)
Stopped
(“H”)
φ BIU, φ CPU
Stopped
(“L”)
Stopped
(“L”)
Stopped
(“L”)
Internal peripheral devices
using Pf2 to Pf512, Wf32,
Wf512
Operation enabled
(Watchdog timer operating)
Operation disabled
(Watchdog timer stopped)
Operation disabled
(Watchdog timer stopped)
Wf2, Wf512
Operating
(Note 2)
Stopped
(“H”)
Stopped
(“H”)
Operation at WIT/STP state
WIT
STP
“0”
“1”
Table 7 Relation between standby state and each block’s operation.
Notes 1 : When the clock external input select bit is “1”, the clock oscillation circuit stops. An external clock can be input.
2 : When the watchdog timer clock select bit is “1”, Wf32 and Wf512 stop. The watchdog timer operates with Pf32 or Pf512.
Operating
(Note 1)
Operating
(Note 1)
Stopped
—
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