參數(shù)資料
型號: M38856F9-HP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 14/103頁
文件大?。?/td> 1580K
代理商: M38856F9-HP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
13
Pin
Name
Input/Output
I/O Structure
Non-Port Function
Ref.No.
Table 6 I/O port function (1)
Related SFRs
I/O PORTS
All I/O pins are programmable as input or output. All I/O ports
have direction registers which specify the data direction of each
pin like input/output. One bit in a direction register corresponds to
one pin. Each pin can be set to be input or output port.
Writing
0
to the bit corresponding to the pin, that pin becomes an
input mode. Writing
1
to the bit, that pin becomes an output
mode.
When the data is read from the bit of the port register correspond-
ing to the pin which is set to output, the value shows the port latch
data, not the input level of the pin. When a pin set to input, the pin
comes floating. In input port mode, writing the port register
changes only the data of the port latch and the pin remains high
impedance state.
When the P8 function selection bit of the port control register 2 is
set to
1
, reading from address 0010
16
reads the port P4 register,
and reading from address 0011
16
reads the port P7 register.
Especially, the input level of P4
2
to P4
6
pins and P7
0
to P7
5
pins
can be read regardless of the data of the direction registers in this
case.
P0
0
-P0
7
P1
0
P1
7
P2
0
/CMP
REF
Port P0
Port P1
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
Analog comparator
power source input pin
Port control register 1
(1)
(2)
Port control register 1
Port control register 2
P2
1
P2
7
P3
0
/PWM
00
P3
1
/PWM
10
Port P2
CMOS compatible
input level
CMOS 3-state output
(3)
(4)
(5)
Port control register 1
AD/DA control register
PWM output
Key-on wake up input
Comparator input
P3
2
P3
7
Port P3
(6)
Key-on wake up input
Comparator input
Port control register 1
P4
0
/X
COUT
P4
1
/X
CIN
P4
2
/INT
0
P4
3
/INT
1
P4
4
/R
X
D
Input/output,
individual bits
(7)
(8)
(9)
(10)
(11)
Sub-clock generating
circuit
CPU mode register
External interrupt input
Interrupt edge selection
register
Port control register 2
Serial I/O control register
Port control register 2
Serial I/O function input
P4
5
/T
X
D
Port P4
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
(12)
Serial I/O control register
UART control register
Port control register 2
Serial I/O function output
P4
6
/S
CLK
(13)
Serial I/O control register
Port control register 2
Serial I/O function I/O
P4
7
/S
RDY
/CLKRUN
Serial I/O control register
Serialized IRQ control
register
Serial I/O function output
Serialized IRQ function
output
(14)
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