參數(shù)資料
型號(hào): M38856F9-HP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 36/103頁
文件大?。?/td> 1580K
代理商: M38856F9-HP
35
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ
= 4 MHz)
Table 10 Multi-master I
2
C-BUS interface functions
Item
Format
Communication mode
System clock
φ
= f(X
IN
)/2 (high-speed mode)
φ
= f(X
IN
)/8 (middle-speed mode)
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 31 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 10 lists the multi-master I
2
C-BUS interface
functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address
register, the I
2
C data shift register, the I
2
C clock control register,
the I
2
C control register, the I
2
C status register, the I
2
C start/stop
condition control register and other control circuits.
When using the multi-master I
2
C-BUS interface, set 1 MHz or
more to system clock
φ
.
Fig. 31 Block diagram of multi-master I
2
C-BUS interface
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
S
CL
clock frequency
I
2
C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
RWB
Noise
elimination
circuit
Serial data
(S
DA
)
Address comparator
b7
I
2
C data shift register
b0
Data
control
circuit
System clock (
φ
)
Interrupt
generating
circuit
Interrupt request signal
(I
2
CIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
S1
b7
b0
TISS
SAD
ALS
BC2 BC1
BC0
S1D
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(S
CL
)
b7
ACKBIT
b0
FAST
Internal data bus
Clock division
S
0
S0D
AL
circuit
ES0
SIS
I
2
C start/stop condition
control register
SIP
SSC4SSC3 SSC2 SSC1 SSC0
I
2
S2
I
2
C status register
S2D
Interrupt
generating
circuit
Interrupt request signal
(S
CL
S
DA
IRQ)
Stop selection
STSP
SEL
CLK
I
2
C clock control register
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