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參數(shù)資料
| 型號： | M38856F9-HP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 30/103頁 |
| 文件大小： | 1580K |
| 代理商： | M38856F9-HP |
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29
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Data Setup (PWM0)
The PWM0 output pin also functions as port P3
0
or P5
6
. The
PWM0 output pin is selected from either P3
0
/PWM
00
or
P5
6
/PWM
01
by PWM
0
output pin selection bit (bit 4 of ADCON).
The PWM0 output becomes enabled state by setting PWM
0
en-
able bit (bit 6 of PCTL1). The high-order eight bits of output data
are set in the PWM0H register and the low-order six bits are set in
the PWM0L register.
PWM1 is set as the same way.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the
high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an
“
H
”
-level
signal is output during each sub-period. There are 64 sub-periods
in each period, and each sub-period is 256
τ
(64
μ
s) long. The
signal is
“
H
”
for a length equal to N times
τ
, where
τ
is the mini-
mum resolution (250 ns).
“
H
”
or
“
L
”
of the bit in the ADD part shown in Figure 24 is added to
this
“
H
”
duration by the contents of the low-order 6-bit data ac-
cording to the rule in Table 9.
That is, only in the sub-period tm shown by Table 9 in the PWM
cycle period T = 64t, its
“
H
”
duration is lengthened to the minimum
resolution
τ
added to the length of other periods.
For example, if the high-order eight bits of the 14-bit data are 03
16
and the low-order six bits are 05
16
, the length of the
“
H
”
-level out-
put in sub-periods t
8
, t
24
, t
32
, t
40
, and t
56
is 4
τ
, and its length is 3
τ
in all other sub-periods.
Time at the
“
H
”
level of each sub-period almost becomes equal,
because the time becomes length set in the high-order 8 bits or
becomes the value plus
τ
, and this sub-period t (= 64
μ
s, approxi-
mate 15.6 kHz) becomes cycle period approximately.
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
at each PWM period (every 4096
μ
s), and data written to the
PWMH register is transferred to the PWM latch at each sub-period
(every 64
μ
s). The signal which is output to the PWM output pin is
corresponding to the contents of this latch. When the PWML reg-
ister is read, the latch contents are read. However, bit 7 of the
PWML register indicates whether the transfer to the PWM latch is
completed; the transfer is completed when bit 7 is
“
0
”
and it is not
done when bit 7 is
“
1
”
.
Table 9 Relationship between low-order 6 bits of data and
period set by the ADD bit
Low-order 6 bits of data (PWML)
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
Sub-periods tm Lengthened (m=0 to 63)
None
m=32
m=16, 48
m=8, 24, 40, 56
m=4, 12, 20, 28, 36, 44, 52, 60
m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63
Fig. 24 PWM timing
4096
μ
s
64
μ
s
64
μ
s
64
μ
s
64
μ
s
m=63
64
μ
s
m=0
m=7
m=9
m=8
15.75
μ
s
15.75
μ
s
15.75
μ
s
16.0
μ
s
15.75
μ
s
15.75
μ
s
15.75
μ
s
Pulse width modulation register H
Pulse width modulation register L
Sub-periods where
“
H
”
pulse width is 16.0
μ
s :
Sub-periods where
“
H
”
pulse width is 15.75
μ
s :
: 00111111
: 000101
m = 8, 24, 32, 40, 56
m = all other values
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