3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
20
INTERRUPTS
Interrupts occur by 16 sources among 22 sources: thirteen exter-
nal, nine internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt caused by the BRK instruction. An interrupt occurs when
both the corresponding interrupt request bit and interrupt enable
bit are
“
1
”
and the interrupt disable flag is
“
0
”
.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction interrupt cannot be disabled with any flag or
bit. The I (interrupt disable) flag disables all interrupts except the
BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
serviced according to the priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table and stored into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the inter-
rupt source selection register (INTSEL).
1. INT
0
or Input buffer full
2. INT
1
or Output buffer empty
3. Serial I/O receive or LRESET
4. Serial I/O transmission or S
CL
S
DA
5. Timer 2 or INT
5
6. CNTR
0
or INT
0
7. CNTR
1
or INT
1
8. A-D conversion or Key-on wake-up
External Interrupt Pin Selection
The external interrupt sources of INT
2
, INT
3
, and INT
4
can be se-
lected from either input pin from INT
20
, INT
30
, INT
40
or input pin
from INT
21
, INT
31
, INT
41
by the INT
2
, INT
3
, INT
4
interrupt switch
bit (bit 4 of PCTL2).
I
Notes
When setting the followings, the interrupt request bit may be set to
“
1
”
.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A
16
); Timer XY mode register (address
0023
16
)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register (address
0039
16
)
When setting input pin of external interrupts INT
2
, INT
3
and INT
4
Related register: INT
2
, INT
3
, INT
4
interrupt switch bit of
P
ort con-
trol register 2 (bit 4 of address 002F
16
)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to
“
0
”
(disabled).
Set the active edge selection bit or the interrupt source selec-
tion bit to
“
1
”
.
Set the corresponding interrupt request bit to
“
0
”
after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to
“
1
”
(enabled).