參數(shù)資料
型號(hào)： M38856F9-HP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 43/103頁(yè)
文件大?。?/td> 1580K
代理商： M38856F9-HP
42
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C START/STOP Condition Control Register
(S2D)] 0017
16
The I
2
C START/STOP condition control register (S2D) controls
START/STOP condition detection.
Bits 0 to 4: START/STOP condition set bits (SSC4
–
SSC0)
S
CL
release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(X
IN
) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 14.
Do not set
“
00000
2
”
or an odd number to the START/STOP condi-
tion set bits (SSC4 to SSC0).
Refer to Table 15, the recommended set value to START/STOP
condition set bits (SSC4
–
SSC0) for each oscillation frequency.
Bit 5: S
CL
/S
DA
interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the S
CL
or S
DA
pin. This bit selects the polarity of the S
CL
or S
DA
pin interrupt pin.
Bit 6: S
CL
/S
DA
interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the S
CL
pin and the S
DA
pin.
Note:
When changing the setting of the S
CL
/S
DA
interrupt pin polarity se-
lection bit, the S
CL
/S
DA
interrupt pin selection bit, or the I
2
C-BUS
interface enable bit ES0, the S
CL
/S
DA
interrupt request bit may be
set. When selecting the S
CL
/S
DA
interrupt source, disable the inter-
rupt before the S
CL
/S
DA
interrupt pin polarity selection bit, the S
CL
/
S
DA
interrupt pin selection bit, or the I
2
C-BUS interface enable bit
ES0 is set. Reset the request bit to
“
0
”
after setting these bits, and
enable the interrupt.
Bit 7: START/STOP condition generating selection bit
(STSPSEL)
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 12 and 13.) Set
“
1
”
to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I
2
C control register (S1D) to
“
0
”
. The first 7-bit address data
transmitted from the master is compared with the high-order 7-
bit slave address stored in the I
2
C address register (S0D). At
the time of this comparison, address comparison of the RWB bit
of the I
2
C address register (S0D) is not performed. For the data
transmission format when the 7-bit addressing format is se-
lected, refer to Figure 42, (1) and (2).
10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I
2
C control register (S1D) to
“
1
”
. An address comparison is
performed between the first-byte address data transmitted from
the master and the 8-bit slave address stored in the I
2
C ad-
dress register (S0). At the time of this comparison, an address
comparison between the RWB bit of the I
2
C address register
(S0) and the R/W bit which is the last bit of the address data
transmitted from the master is made. In the 10-bit addressing
mode, the RWB bit which is the last bit of the address data not
only specifies the direction of communication for control data,
but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I
2
C status register (S1) is set to
“
1
”
. After the
second-byte address data is stored into the I
2
C data shift reg-
ister (S0), perform an address comparison between the
second-byte data and the slave address by software. When the
address data of the 2 bytes agree with the slave address, set
the RWB bit of the I
2
C address register (S0D) to
“
1
”
by soft-
ware. This processing can make the 7-bit slave address and R/
___
W data agree, which are received after a RESTART condition
is detected, with the value of the I
2
C address register (S0D).
For the data transmission format when the 10-bit addressing
format is selected, refer to Figure 42, (3) and (4).
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