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參數(shù)資料
| 型號： | M48Z19-100PC1 |
| 廠商： | 意法半導體 |
| 英文描述： | CMOS 8K x 8 ZEROPOWER SRAM |
| 中文描述： | 的CMOS 8K的× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 122K |
| 代理商： | M48Z19-100PC1 |
Symbol
Parameter
Min
Max
Unit
t
PD
E1 or W at V
IH
or E2 at V
IL
before Power Down
0
μ
s
t
F (1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
μ
s
t
FB (2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
μ
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
0
μ
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
1
μ
s
t
REC
E1 or W at V
IH
or E2 at V
IL
after Power Up
1
ms
t
PFX
INT Low to Auto Deselect
10
40
μ
s
t
PFH(3)
V
PFD
(max) to INT High
120
μ
s
Notes
: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
μ
s after
V
CC
passes V
PFD
(min).
2. V
(min) to V
fall time of less than t
may cause corruption of RAM data.
3. INT may go high anytime after V
CC
exceeds V
PFD
(min) and is guaranteed to go high t
PFH
after V
CC
exceeds V
PFD
(max).
Table 7. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
°
C)
AI00566
VCC
VPFD (max)
INPUTS
INT
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tPFX
tR
tPFH
tREC
tPD
tRB
tDR
VALID
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (min)
VSO
Figure 5. Power Down/Up Mode AC Waveforms
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E1
high or E2 low as V
rises past V
(min).
Some systems may performs inadvertent write cycles after V
rises above V
(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/13
M48Z09, M48Z19
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