參數(shù)資料
型號: M58LW128A150N1
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 150 ns, PDSO56
封裝: 14 X 20 MM, PLASTIC, TSOP-56
文件頁數(shù): 56/65頁
文件大?。?/td> 378K
代理商: M58LW128A150N1
M58LW128A, M58LW128B
6/65
SUMMARY DESCRIPTION
M58LW128 is a 128 Mbit (8Mb x16 or 4Mb x32)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply. On power-up the memory defaults to
Read mode with an asynchronous bus where it
can be read in the same way as a non-burst Flash
memory.
The memory is divided into 128 blocks of 1Mbit
that can be erased independently so it is possible
to preserve valid data while old data is erased.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram up to 16 Words (or 8 Double Words) in par-
allel, both speeding up the programming and
freeing up the microprocessor to perform other
work. The minimum buffer size for a program op-
eration is an 8 Word (or 4 Double Word) page. A
page can only be programmed once between
Erase operations.
Erase can be suspended in order to perform either
read or program in any other block and then re-
sumed. Program can be suspended to read data in
any other block and then resumed. Each block can
be programmed and erased over 100,000 cycles.
Individual block protection against program or
erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All program or erase opera-
tions are blocked when the Program Erase Enable
input Vpp is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in Power-Down mode. It can also be used to
temporarily disable the protection mechanism.
In asynchronous mode Chip Enable, Output En-
able and Write Enable signals control the bus op-
eration of the memory. An Address Latch input can
be used to latch addresses in Latch Controlled
mode. Together they allow simple, yet powerful,
connection to most microprocessors, often without
additional logic.
In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out-
put Enable select the Bus Read operation; the ad-
dress is Latched using the Latch Enable inputs
and the address is advanced using Burst Address
Advance. The signals are compatible with most
microprocessor burst interfaces.
A One Time Programmable (OTP) area is included
for security purposes. Either 1K Words (x16 Bus
Width) or 1K Double-Words (x32 Bus Width) is
available in the OTP area. The process of reading
from and writing to the OTP area is not published
for security purposes; contact STMicroelectronics
for details on how to use the OTP area.
The memory is offered in various packages. The
M58LW128A is available in TSOP56 (14 x 20 mm)
and TBGA64 (1mm pitch). The M58LW128B is
available in TBGA80 (1mm pitch).
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