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參數(shù)資料
| 型號： | M58LW64D |
| 廠商： | 意法半導體 |
| 英文描述： | 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| 中文描述： | 64兆位（和8Mb × 8，4Mb的x16插槽，統(tǒng)一座）3V電源快閃記憶體 |
| 文件頁數(shù)： | 12/50頁 |
| 文件大小： | 783K |
| 代理商： | M58LW64D |
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M58LW064D
12/50
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Power-Down and Standby. See
Table
3., Bus Operations
, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read.
Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to
Table 2., Device Enable
), applying a
Low signal, V
IL
, to Output Enable and keeping
Write Enable High, V
IH
. The data read depends on
the previous command written to the memory (see
Command Interface section).
See Figures
9
and
10
Read AC Waveforms, and
Tables
15
and
16
Read AC Characteristics, for de-
tails of when the output becomes valid.
Bus Write.
Bus Write operations write Com-
mands to the memory or latch addresses and input
data to be programmed.
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and en-
abling the device (refer to Chip Enable section).
The Address Inputs are latched by the Command
Interface on the rising edge of Write Enable or the
first edge of E0, E1 or E2 that disables the device
(refer to
Table 2., Device Enable
).
The Data Input/Outputs are latched by the Com-
mand Interface on the rising edge of Write Enable
or the first edge of E0, E1 or E2 that disable the de-
vice whichever occurs first. Output Enable must
remain High, V
IH
, during the Bus Write operation.
See Figures
11
and
12
, Write AC Waveforms, and
Tables
17
and
18
, Write and Chip Enable Con-
trolled Write AC Characteristics, for details of the
timing requirements.
Output Disable.
The Data Inputs/Outputs are
high impedance when the Output Enable is at V
IH
.
Power-Down.
The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
DD2
, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
Standby.
Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
when Chip Enable is at V
IH
. The power consump-
tion is reduced to the standby level I
DD1
and the
outputs are set to high impedance, independently
from the Output Enable or Write Enable inputs.
If Chip Enable switches to V
IH
during a program or
erase operation, the device enters Standby mode
when finished.
Table 3. Bus Operations
Note: 1. DQ8-DQ15 are High Z in x8 mode.
2. X = Don’t Care V
IL
or V
IH.
Operation
E0, E1
or E2
G
W
RP
A1-A22 (x16)
A0-A22 (x8)
DQ0-DQ15 (x16)
DQ0-DQ7 (x8)
(1)
Bus Read
V
IL
V
IL
V
IH
V
IH
Address
Data Output
Bus Write
V
IL
V
IH
V
IL
V
IH
Address
Data Input
Output Disable
V
IL
V
IH
V
IH
V
IH
X
High Z
Power-Down
X
X
X
V
IL
X
High Z
Standby
V
IH
X
X
V
IH
X
High Z
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