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參數(shù)資料
| 型號： | M66244FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | High Speed Monolithic Pulse Width Modulator |
| 中文描述： | 單片高速脈寬調(diào)制器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 78K |
| 代理商： | M66244FP |
High Speed Monolithic Pulse Width Modulator
TEST CIRCUIT DESCRIPTION (JTAG)
GENERAL DESCRIPTION
The Test Access Port conforms with the IEEE standard 1149.1.
This standard defines a test access port and boundary-scan architecture for digital integrated
circuits.
The facilities defined by the standard seek to provide a solution to the problem of testing
assembled printed circuit boards and other products based on highly complex digital
integrated circuits and high-density surface-mounting assembly techniques. They also
provide a means of accessing and controlling design-for-test features build into digital
integrated circuits themselves.
PIN DESCRIPTION
TCK,TMS,TDI,TRST,TDO are used in this test operation.
Test Clock Input (TCK)
TCK provides the clock for the test logic defined by this standard. Stored-state devices
contained in the test logic retain their state indefinitely when the signal applied to TCK is
stopped at 0.
Test Mode Select Input (TMS)
The signal received at TMS is decoded by the TAP controlled to control test operation.
The signal presented at TMS is sampled by the test logic on the rising edge of TCK.
Test Data Input (TDI)
Serial test instructions and data are received by the test logic at TDI.
The signal presented at TDI is sampled by the test logic on the rising edge of TCK.
Test Reset Input (TRST)
The TRST input provides for asynchronous initialization of the TAP controller.
If TRST is included in the TAP, then the TAPcontroller is asynchronously reset to the Test-
Logic-Reset controller state when a logic 0 is applied to TRST.
Test Data Input (TDO)
TDO is a serial output for test instructions and data from the test logic defined in this
standard.
Changes in the state of the signal driven through TDO occur only on the falling edge of
TCK. The TDO driver is set to its inactive drive state except when the scanning of data is in
progress.
MITSUBISHI <DIGITAL ASSP>
M66244FP
(11/15)
C 1998 MITSUBISHI ELECTRIC CORPORATION
June 1998 Ver.8.0.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66250 | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250FP | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250P | 5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66252FP | 1152 x 8-BIT LINE MEMORY FIFO |
| M66252P | 1152 x 8-BIT LINE MEMORY FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66250 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120*8-BIT LINE MEMORY(FIFO/LIFO) |
| M66250P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120*8-BIT LINE MEMORY(FIFO/LIFO) |
| M66252FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
| M66252P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
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