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參數(shù)資料
| 型號： | M66244FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | High Speed Monolithic Pulse Width Modulator |
| 中文描述： | 單片高速脈寬調(diào)制器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 78K |
| 代理商： | M66244FP |
MITSUBISHI <DIGITAL ASSP>
M66244FP
High Speed Monolithic Pulse Width Modulator
OPERATING TIMING
EXAMPLE
DATA(D<0:5>) and CONTROL(SEM/DEM,LEM/TEM) are written to the latching circuit at the
first rise edge of CLK. PWMOUT is outputted at the next edge of CLK. A propagation delay
exists between the CLK and PWMOUT pulse. The minimum propagation delay can be observed
when alternating between codes 00(H) and 3F(H).
In the following diagram, when SET is "H" , PWM output is "H" , when SET is "L" , PWMOUT is
determined correspond to D<5:0>. The function of SET is direct set, so when the rise edge of
CLK and SET are entered at the same time PWMOUT will be "H" .
(6/15)
C 1998 MITSUBISHI ELECTRIC CORPORATION
CLK
D<5:0>
SEM/DEM
LEM/TEM
n+3
n+2
n+1
n
tsu(D)
th(D)
tsu(SD)
th(SD)
tsu(LT)
th(LT)
tw(CLK)
n+3
n+2
n+1
n
n+3
n+2
n+1
n
PWMOUT
td(PWM)
td(SET)
SET
n
"H"
td(PWM)
n+3
N cycle
N+1 cycle
N+2 cycle
N+3 cycle
N
cycle output
N+3
cycle output
N+4 cycle
n+3
n+3
n+3
tw(SET)
td(SET)
June 1998 Ver.8.0.0
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| M66250 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 X 8-BIT LINE MEMORY(FIFO/LIFO) |
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| M66250P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120*8-BIT LINE MEMORY(FIFO/LIFO) |
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| M66252P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
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