- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370992 > M66256 (Mitsubishi Electric Corporation) 5120 x 8-BIT LINE MEMORY (FIFO) PDF資料下載
參數(shù)資料
| 型號(hào)： | M66256 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 5120 x 8-BIT LINE MEMORY (FIFO) |
| 中文描述： | 5120 × 8位列內(nèi)存（先進(jìn)先出） |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | M66256 |
1
M66256FP
5120
8-BIT LINE MEMORY (FIFO)
5120
×
8-BIT LINE MEMORY (FIFO)
MIMITSUBISHI
DIDIGITAL ASSP
DESCRIPTION
The M66256FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word
×
8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
FEATURES
Memory configuration ........................................................
............................. 5120 words
×
8-bits (dynamic memory)
High-speed cycle ............................................. 25ns (Min.)
High-speed access ......................................... 18ns (Max.)
Output hold ........................................................ 3ns (Min.)
Fully independent, asynchronous write and read operations
Variable length delay bit
Output ....................................................................3 states
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
DATA INPUT
DATA OUTPUT
DATA OUTPUT
DATA INPUT
24
13
14
15
16
17
18
19
20
21
22
READ ENABLE INPUT
WRITE ENABLE INPUT
WRITE RESET INPUT
WRITE CLOCK INPUT
READ RESET INPUT
READ CLOCK INPUT
M
23
1
11
12
10
9
8
7
6
5
4
3
2
Q
0
←
Q
1
←
Q
2
←
Q
3
←
RE
→
RRES
→
GND
RCK
→
Q
4
←
Q
5
←
Q
6
←
Q
7
←
←
D
0
←
D
1
←
D
2
←
D
3
←
WE
←
WRES
←
WCK
V
CC
←
D
4
←
D
5
←
D
6
←
D
7
20
MEMORY ARRAY OF
5120-WORD
×
8-BIT
CONFIGURATION
W
R
R
W
19
17
18
WE
WRES
WCK
V
CC
WRITE
ENABLE INPUT
WRITE
RESET INPUT
WRITE
CLOCK INPUT
5
6
8
7
RE
RRES
RCK
GND
READ
ENABLE INPUT
READ
RESET INPUT
READ
CLOCK INPUT
13
INPUT BUFFER
DATA INPUT
D
0
~
D
7
OUTPUT BUFFER
14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
DATA OUTPUT
Q
0
~
Q
7
Outline 24P2U-A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66256FP | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66257 | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 8192 x 8-BIT LINE MEMORY |
| M66258FP | 8192 x 8-BIT LINE MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66256FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit Line Memory (FIFO) |
| M66256FP(#TF0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66257 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。