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參數(shù)資料
| 型號： | M66256 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 5120 x 8-BIT LINE MEMORY (FIFO) |
| 中文描述： | 5120 × 8位列內(nèi)存（先進先出） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 148K |
| 代理商： | M66256 |
8
MITSUBISHI
DIGITAL ASSP
M66256FP
5120
×
8-BIT LINE MEMORY (FIFO)
VARIABLE LENGTH DELAY BITS
1-line (5120 bits) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
N-bit delay bit
(Making a reset at a cycle corresponding to delay length)
t
DS
t
DH
t
DS
t
OH
t
AC
m cycles
t
DH
t
RESS
t
RESH
t
RESS
t
RESH
(0)
Cycle 0
Cycle 1
Cycle 2
Cycle n–2
Cycle n–1
Cycle n
(0')
Cycle n+1
(1')
Cycle n+2
(2')
Cycle n+3
(3')
WCK
RCK
D
n
Q
n
WE, RE = “L”
3
m
≥
WRES
RRES
(1)
(2)
(n–3)
(n–2)
(n–1)
(0')
(1')
(2')
(3')
(0)
(1)
(2)
(3)
t
DS
t
DH
t
DS
t
OH
t
AC
5120 cycles
t
DH
t
RESS
t
RESH
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
(0)
(1)
(2)
(3)
Cycle 0
Cycle 1
Cycle 2
Cycle 5118 Cycle 5119
Cycle 5120
(0')
Cycle 5121
(1')
Cycle 5122
(2')
WCK
RCK
WRES
RRES
WE, RE = “L”
D
n
Q
n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66256FP | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66257 | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 8192 x 8-BIT LINE MEMORY |
| M66258FP | 8192 x 8-BIT LINE MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66256FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit Line Memory (FIFO) |
| M66256FP(#TF0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66257 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
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