參數(shù)資料
型號: M66290AGP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: LQFP-48
文件頁數(shù): 12/53頁
文件大?。?/td> 435K
代理商: M66290AGP
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
2
Xin
CS
RD
WR
INT
Dreq
68
D+
D-
GND
2 15 36
Clock
Control
(Oscillator/
PLL)
Serial
Interface
Engine
Device
Control
Unit
A6 to 1
CPU
Register
Endpoint
Buffer
(3KByteFIFO)
USB
Peripheral
Circuit
Dack
VCC
1 16 35
4
3
Vbus
13
14
6
T rON
5
Xout
45
44
43
42
17
22
23
40
D15 to 0
68
47
48
46
41
7
RST
TEST2
TEST1
8
9
10
11
12
TRST
TCK
T MS
TDI
TDO
to
BLOCK DESCRIPTIONS
The M66290A contains USB transceiv er, oscillation
circuit, PLL, serial interf ace engine, endpoint buff er,
dev ice control unit, and CPU register.
USB Transceiv er
USB Transceiv er is consisted of diff erential driv er
and diff erential receiv er.
And is compatible with USB specif ication v ersion 1.1
and corresponds to Full Speed Transf er mode.
Serial Interf ace Engine (SIE)
SIE handles protocol lay er as f ollows.
Extract a USB 12MHz clock
Serial-Parallel data conv ersion
SYNC detection
NRZI encode and decode
Bit stuff ing and destuff ing
CRC generator and checker
Dev ice Control Unit (DCU)
DCU controls the dev ice state sequence, control
transf er sequence, and so on.
Endpoint Buff er
This is a FIFO buff er f or transmit and receive
between endpoints.
Except f or EP0 f or control transf er, f iv e endpoints
(EP1 to EP5) can be set.
CPU Register
This is an interf ace block with CPU.
Oscillator/PLL
This block oscillates the internal operation clock
source of 48MHz.
External clock of 6/12/24/48MHz can be input.
USB peripheral circuit
Detect the connection and the shutdown of USB
by the Vbus input.
Connect the Vbus of U SB bus to or the 5V power
supply to Vbus input.
Connect the TrON output to D+ pull-up resistor of
1.5kohm. ON/OFF of the pull-up resistor is controlled
by the register.
BLOCK DIAGRAM
USB
Transceiver
to
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66291GP 制造商:Renesas Electronics Corporation 功能描述:
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