參數(shù)資料
型號(hào)： M66290AGP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： LQFP-48
文件頁(yè)數(shù)： 13/53頁(yè)
文件大?。?/td> 435K
代理商： M66290AGP
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
20
(3) Control transfer / Enumeration
In control transf er, there are setup stage, data stage,
and status stage.
M66290A manages stage and inf orm CPU the stage
shif t by interrupt. CPU do stage transact of control
transf er according to the interrupt f actor.
Setup stage
In setup stage, 8By tes request (setup data) of setup
transaction data packet which transf erred f rom host
is stored into f our registers automatically (Request,
Value, Index, and Length register).
Except f or dev ice state shif t request (Set Address and
Set Conf iguration) which can cope with by the automatic
response control f unction, analy sis (decode) and
execution of contents of request must be done by CPU.
By executing the request, it proceeds to data stage or
to status stage.
Data stage
Data stage executes IN transaction or OUT transaction
according to the contents of request. If it is control
write transf er, data stage is OUT transaction and CPU
prepares f or data receiv e at the timing of interrupt in
setup stage and reads the receiv ed data f rom endpoint
FIFO when data receiv e ended.
USB bus connect
Full speed
dev ice recognition
Clock ON
Initializing
Tr ON
Vbus interrupt
USB reset
USB reset receive
DVST interrupt
USB request
(Control transf er)
Get xx command
CTRT interrupt
Set response data
USB request
Set Address
CTRT/DVST interrupt
(Automatic response av ailable)
USB request
Get xx command
CTRT interrupt
Set Conf iguration
CTRT/DVST interrupt
(Automatic response av ailable)
USB request
Set xx command
CTRT interrupt
Set response data
Read receiv ed data
Def ault
state
Address
state
Conf igured
state
Idle
(Powered)
If it is control read transf er, data stage is IN transaction
and CPU prepares f or data transmit (write into endpoint
FIFO) at the timing of interrupt in setup stage.
M66290A is equipped with control transf er continuous
transmit and receiv e f unction. Af ter ended data stage,
it proceeds to status stage.
M66290A
Dev ice f irmware
Dev ice state
Figure 3. Abstract of enumeration operations
Status stage
Status stage executes receiv e/transmit of N ull data
(data length 0), in both control write and control read
transf er. Receiv e/transmit of N ull data is possible to
set control transf er complete enable bit (CCPL) af ter
ended setup stage.
Control transf er complete enable bit is reset when
receiv ed setup packet.
Control transf er executes data transf er using EP0.
To both control read and control write, buff er size of
EP0 can be set by a unit of 64By tes by "Control
Transf er Control Register".
Access to EP0_FIFO data register must be done by
CPU access. DMA transf er can not be set.
Figure 3. shows the abstract of enumeration
operations.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66291GP 制造商:Renesas Electronics Corporation 功能描述:
M66291GP#201 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP
M66291GP#RB0S 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
M66291GPRB0S 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48
M66291HP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller)
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