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參數(shù)資料
| 型號： | M66290AGP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 8/53頁 |
| 文件大?。?/td> | 435K |
| 代理商： | M66290AGP |
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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
16
Bit
Name
Function
Reset
-
0
R
This bit changes to "1" at the timing of token packet receive end when
buffer respond NAK, of its not ready state, to IN/OUT token of each
endpoint.
The endpoint which occurred the interrupt is checked to see
EPB_NRDY[5:0].
This flag is cleared to clear the status flag of EPB_NRDY[5:0].
Endpoint5-0 buffer
not ready
interrupt enable
INTN
9
-
0
R
This bit changes to "1" when the buffer of each endpoint
became ready (read/write enable).
The endpoint which occurred the interrupt is checked to see
EPB_RDY[5:0].
This flag is cleared to clear the status flag of
EPB_RDY[5:0].
Endpoint5-0 buffer
ready
interrupt enable
INTR
8
R
W/R
R
-
0
-
000
001
000
Ext.
R
000: Powered State
001: Default State
010: Address State
011: Configured State
1xx: Suspended State
Device state can be known.
As to the device state shift, refer to Fig.5 in the later part.
When detect USB reset, this becomes 001: Default state automatically.
When detect suspend, this becomes 1xx: Suspended state automatically.
Whatever the automatic response mode is, this becomes 010: Address
state after executed Set_Address request, and becomes 011: Configured
state after executed Set_Configuration request.
(Write operation is available when S/W control mode is set)
Device state
This bit changes to "1" when received setup packet.
This flag does not the factor of interrupt.
When "0" is written, status flag is cleared .
When "1" is written, flag is not changed .
Setup packet
detect
000 : Idle or Setup stage
001 : Control read transfer data stage
010 : Control read transfer status stage
011 : Control write transfer data stage
100 : Control write transfer status stage
101 : Control write no data transfer status stage
110 : Control transfer sequence error
111 : Not assigned
Can be seen the stage of control transfer.
As to the stage shift of control transfer, refer to Fig.5 in the later part.
(Write operation is available when S/W control mode is set)
Control transfer
Stage
2-0
Vbus input port
Input data from external Vbus is stored.
0: Vbus input port is "L"
1: Vbus input port is "H"
External Vbus input data is latched by the positive edge of internal clock.
Refer to this bit after enabled internal clock operation.
7
DVSQ
[2:0]
3
6-4
CTSQ
[2:0]
VALID
Vbus
W/R
USB
S/W
H/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP | 制造商:Renesas Electronics Corporation 功能描述: |
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
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