參數(shù)資料
型號(hào): M66290AGP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: LQFP-48
文件頁(yè)數(shù): 43/53頁(yè)
文件大小: 435K
代理商: M66290AGP
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
48
D15 to 0
Dreq
tsu(D)
tw(CTRL)
th(D)
twh(Dreq)
td(Dack-Dreq)
D15 to 0
ten(CTRL)
tw(CTRL)
tdis(CTRL)
tv(CTRL)
ta(CTRL)
RD
WR
(4) DMA Transfer Timing -2
(4-2) Read timing -1
Dack
Dreq
twh(Dreq)
td(Dack-Dreq)
Dack
trec(CTRL)
td(Dackh-Dreq)
Data output is established
Data input is established
(note 7)
(note 6)
(note 7)
(note 5)
note 7 : Inactive condition of Dreq is Dack="L"
And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(Dackh-Dreq).
note 5 : Write is done in the overlap period when Dack and WR is active "L".
Spec from the positive edge is valid from the fastest inactive signal.
Spec of pulse width is valid of the overlap period of active "L".
note 6 : Read is done in the overlap period of Dack and RD is active "L"
Spec from the negative edge is valid from the latest signal.
Spec from the positive edge is valid form the fastest inactive signal.
Spec of pulse width is valid during active "L" overlap period.
In case of one word transfer mode (DMA operation mode register : MODE=1)
(4-1) Write timing -1
td(Dackh-Dreq)
td(CTRL-Dack)
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