參數(shù)資料
型號(hào)： M66335FP
廠商： Mitsubishi Electric Corporation
英文描述： FACSIMILE IMAGE DATA PROCESSOR
中文描述： 傳真寄發(fā)圖像數(shù)據(jù)處理器
文件頁(yè)數(shù)： 37/57頁(yè)
文件大?。?/td> 656K
代理商： M66335FP
37
MITSUBISHI
DIGITAL ASSP
M66335FP
FACSIMILE IMAGE DATA PROCESSOR
(2) Line clamping circuit
This circuit is used for CCD (line clamping mode) and CIS3.
The reference voltage (dark voltage) output in the shielding pixel part
of the sensor is sampled by LCMP (line clamping pulses) and shifted
up to the internal reference voltage of 2.2V. This is not used for the
CIS1 or CIS2 input sensor (set off constantly).
: register 02 (LCMPS)
(3)
Sample and hold circuit and bit clamping circuit
In the CCD mode, bit clamping, as well as line clamping, can be
performed. The blanking elements of each pixel of sensor output is
sampled by BTCMP (bit clamping pulses). The differences of signals
from the reference potential sampled by the bit clamping circuit are
input to the gain control circuit of next step as signaling elements. To
turn off bit clamping, set BLS invalid, so that the reference potential
will be fixed at the internal reference potential of 2.2V.
: register 02 (BLS)
(4) Gain control circuit
The amplifying factor (gain) must be adjusted so that the amplitudes
of sensor signals can come within the dynamic range of the A/D con-
verter. The gain is set through the automatic gain control in the AGC
mode (register 00) or directly through the register 18 (GAIN <7 : 0>).
The gain changes within the following ranges according to the sen-
sor used.
In the AGC mode, the gain control counter is set at the greatest gain
in the initial state and then counted down each time an overflow bit is
output from the A/D converter. The count (gain) of the gain control
counter is directly read/written through the register 18 (GAIN
<7 : 0>). The counting operation of the counter can be controlled
through the register 16 (AGCSTP).
(5) Internal reference voltage
Internal reference voltage source for the analog circuits:
this generates the reference voltage (2.2V) for the line clamping
circuit, the sample and hold circuit, and the bit clamping circuit.
A/D converter reference voltage generation circuit:
this generates VWL (white level reference voltage of 3.8V) and
VBL (black level reference voltage of 1.8V) for the A/D converter.
Amplifying factor of signals (gain)
4 to 20
0.5 to 2.5
1 to 5
1 to 5
Mode
CCD
CIS1
CIS2
CIS3
(6) Black level clamping circuit
This circuit adjust the level of reference voltage to the A/D converter
from analog circuits.
The black clamping circuit is used in the CCD or CID3 mode. (See
Figs. 18, 19 and 22) The GCAO pin and the BCMI pin are capacity-
coupled. The output reference potential in the shielding pixel part of
sensor signals are applied to the BCMV pin as the VBL (black level
reference voltage of 1.8V) for the A/D converter.
BLCMP (black level clamping pulses) are generated concurrently with
the shielding pixel part of each line. To turn off this circuit, set BLCMPS
invalid and apply the black level reference voltage of the A/D con-
verter to the BCMV pin.
In the CIS1 or CIS2 mode, the LEVAJ pin is used. (See Figs. 20 and
21) Voltage is applied to the LEVAJ pin so that the reference poten-
tial of output at the GCAO pin can be adjusted to the VBL (black level
reference voltage of 1.8V) of the A/D converter. Set voltage input to
the LEVAJ pin as follows.
VLEVAJ = VVBL – A
×
G
V
+ 0.2 [V]
VGCAO = VLEVAJ + G
V
×
VIN [V]
where,
A: the lowest limit of dark voltage of the sensor [V]
G
V
: gain (multiplying factor) of the gain control circuit
V
IN
: signals input from the sensor [V]
: register 02 (BLCMPS)
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