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參數(shù)資料
| 型號： | M66335FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FACSIMILE IMAGE DATA PROCESSOR |
| 中文描述： | 傳真寄發(fā)圖像數(shù)據(jù)處理器 |
| 文件頁數(shù)： | 9/57頁 |
| 文件大小： | 656K |
| 代理商： | M66335FP |
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9
MITSUBISHI
DIGITAL ASSP
M66335FP
FACSIMILE IMAGE DATA PROCESSOR
Fig. 2 CODEC interface operations and the reading sequence (Binary data output : sirial output)
Fig. 3 DMA interface operations and the reading sequence (Multivated data output)
ACCK
SH
SRDYB
<SRDYB>
(SSCAN)
INT
SCLK
SVID
PTIMB
STIMB
1
SRDYB : ‘L’ is taken in with a
↑
flow of SH, when scanning is started and PTIMB is output. (SSCAN : ‘H’)
2
During the period that STIMB is ‘L’, converted binary data are output.
3
SRDYB : ‘H’ is taken in with a
↑
flow of ACCK, when the reading of one line ends. (SSCAN : ‘L’)
4
INT is asserted with a
↓
flow of SSCAN. (INT : ‘H’)
5
When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set ‘L’.
(SSCAN) : Internal signal
1
2
3
4
: Output section
<INTCLR>
<INTCLR> : Register setting
5
ACCK
SH
<SRDYB>
(SSCAN)
INT
DRQ
DAKB
RDB
PTIMB
(DMAFIN)
<INTCLR>
(Counter reset)
1
SRDYB : ‘L’ is taken in with a
↑
flow of SH, when scanning is started and PTIMB is output. (SSCAN : ‘H’)
2
SRDYB : ‘H’ is taken in with a
↑
flow of ACCK, when the reading of one line ends. (SSCAN : ‘L’)
3
The internal counter reset signal is generated with a
↓
flow of SSCAN, and DRQ is asserted with a
↑
flow of SSCAN.
4
After the internal counter is reset, DMA transfer is started. (The internal counter is counted up by one each time a
pixel is transferred.)
5
When the value of the internal counter reaches the output pixel number, DMAFIN shifts to ‘H’, and DRQ is negated
with a
↑
flow form DMAFIN and INT is asserted with a
↓
flow of DMAFIN.
6
When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set ‘L’.
(SSCAN), (DMAFIN), (counter reset) : Internal signal
<SRDYB>, <INTCLR> : Register setting
1
2
3
4
5
6
: Output section
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