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參數(shù)資料
| 型號： | M68HC11D3CFB1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 109/124頁 |
| 文件大?。?/td> | 5398K |
| 代理商： | M68HC11D3CFB1 |
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SERIAL PERIPHERAL INTERFACE
TECHNICAL DATA
8-7
8.5.2 Serial Peripheral Status
SPIF — SPI Transfer Complete Flag
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless
SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.
WCOL — Write Collision
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) fol-
lowed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
0 = No write collision
1 = Write collision
Bit 5 — Not implemented
Always reads zero
MODF — Mode Fault
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not implemented
Always read zero
8.5.3 Serial Peripheral Data I/O
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
NOTE
SPI is double buffered in and single buffered out.
SPSR — Serial Peripheral Status Register
$0029
Bit 7
654321
Bit 0
SPIF
WCOL
0
MODF
0000
RESET:
00000000
SPDR — SPI Data Register
$002A
Bit 7
654321
Bit 0
Bit 7
654321
Bit 0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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