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參數(shù)資料
| 型號： | M7040N-083ZA1T |
| 廠商： | 意法半導體 |
| 英文描述： | CAP 5600PF 100V 10% X7R AXIAL BULK P-MIL-PRF-39014 |
| 中文描述： | 64K的× 72位的網(wǎng)絡數(shù)據(jù)包進入搜索引擎 |
| 文件頁數(shù)： | 120/159頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-083ZA1T |
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M7040N
120/159
LEARN COMMAND
Bit [0] of each 72-bit data location specifies wheth-
er an entry in the database is occupied. If all the
entries in a device are occupied, the device as-
serts FULO signal to inform the downstream de-
vices that it is full.
The result of this communication between depth-
cascaded devices determines the global FULL
signal for the entire table. The FULL signal in the
last device determines the fullness of the depth-
cascaded table.
In a depth-cascaded table, only a single device will
learn the entry through the application of a LEARN
Instruction. The determination of which device is
going to learn is based on the FULI and FULO sig-
nalling between the devices. The first non-full de-
vice learns the entry by storing the contents of the
specified comparand registers to the location(s)
pointed to by NFA.
In a x72-configured table the LEARN command
writes a single 72-bit location. In a x144-config-
ured table the LEARN command writes the next
even and odd 72-bit locations. In 144-bit mode,
Bit[0] of the even and odd 72-bit locations is '0,'
which indicates they are cascaded empty, or '1,'
which indicates they are occupied.
The global FULL signal indicates to the Table Con-
troller (the host ASIC) that all entries within a block
are occupied and that no more entries can be
learned. The M7040N updates the signal after
each WRITE or LEARN command to a data array.
The LEARN command generates a WRITE cycle
to the external SRAM, also using the NFA register
as part of the SRAM address (see SRAM AD-
DRESSING, page 128).
The LEARN command is supported on a single
block containing up to eight devices if the table is
configured either as a x72 or a x144. The LEARN
command is not supported for x288-configured ta-
bles.
LEARN is a pipelined operation and lasts for two
CLK cycles, as shown in Figure 90, page 121
where TLSZ = 00, and Figure 91, page 122 and
Figure 92, page 123 where TLSZ = 01 (which as-
sume the device performing the LEARN operation
is not the last device in the table and has its LRAM
Bit set to '0.'
Note:
The OE_L for the device with the LRAM Bit
set goes high for two cycles for each LEARN (one
during the SRAM WRITE cycle, and one the cycle
before). The latency of the SRAM WRITE cycle
from the second cycle of the Instruction is shown
in Table 51, page 123.
The sequence of operation is as follows:
–
Cycle 1A
: The host ASIC applies the LEARN In-
struction on the CMD[1:0], using CMDV = 1.
The CMD[5:2] field specifies the index of the
comparand register pair that will be written in
the data array in the 144-bit-configured table.
For a LEARN in a 72-bit-configured table, the
even-numbered comparands specified by this
index will be written. CMD[8:6] carries the bits
that will be driven on SADR[23:21] in the SRAM
WRITE cycle.
–
Cycle 1B
: The host ASIC continues to drive
CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2]
with the comparand pair index. CMD[6] must be
set to '0' if the LEARN is being performed on a
72-bit-configured table, and to '1' if the LEARN
is being performed on a 144-bit-configured ta-
ble.
–
Cycle 2:
The host ASIC drives the CMDV to '0.'
At the end of Cycle 2, a new instruction can be-
gin. The latency of the SRAM WRITE is the
same as the search to the SRAM READ Cycle.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M7040N-100ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M7041 | 制造商:Tamura Corporation of America 功能描述: |
| M7045 | 制造商:Tamura Corporation of America 功能描述: |
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