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參數(shù)資料
| 型號： | M7040N-083ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 5600PF 100V 10% X7R AXIAL BULK P-MIL-PRF-39014 |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁數(shù)： | 75/159頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | M7040N-083ZA1T |
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M7040N
The following is the sequence of operation for a
single 144-bit SEARCH command (see COM-
MAND CODES AND PARAMETERS, page 30).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
for use in this SEARCH operation. CMD[8:6]
signals must be driven with the bits that will be
driven on SADR[23:21] by this device if it has a
hit. DQ[71:0] must be driven with the 72-bit data
([143:72]) in order to be compared against all
even locations. The CMD[2] signal must be driv-
en to logic '0.'
–
Cycle B:
The host ASIC continues to drive the
CMDV high and to apply SEARCH command
code ('10') on CMD[1:0]. CMD[5:2] must be driv-
en by the index of the comparand register pair
for storing the 144-bit word presented on the DQ
Bus during Cycles A and B. CMD[8:6] signals
must be driven with the index of the SSR that
will be used for storing the address of the
matching entry and the Hit Flag (see SEARCH-
Successful Registers (SSR[0:7]), page 24). The
DQ[71:0] is driven with 72-bit data ([71:0]) to be
compared against all odd locations.
The logical 144-bit search operation is as shown in
Figure 54, page 78. The entire table of 31 devices
(consisting of 144-bit entries) is compared against
a 144-bit word K that is presented on the DQ Bus
in Cycles A and B of the command using the GMR
and local mask bits. The GMR is the 144-bit word
specified by the even and odd global mask pair se-
lected by the GMR Index in the command
’
s Cycle
A.
The 144-bit word K that is presented on the DQ
Bus in Cycles A and B of the command is also
stored in the even and odd comparand registers
specified by the Comparand Register Index in the
command
’
s Cycle B. In x144 configurations, the
even and odd comparand registers can subse-
quently be used by the LEARN command in only
the first non-full device.
Note:
The LEARN command is supported for only
one of the blocks consisting of up to eight devices
in a depth-cascaded table of more than one block.
The word K that is presented on the DQ Bus in Cy-
cles A and B of the command is compared with
each entry in the table starting at location
“
0.
”
The
first matching entry
’
s location address,
“
L,
”
is the
winning address that is driven as part of the SRAM
address on the SADR[23:0] lines (see SRAM AD-
DRESSING, page 128). The global winning device
will drive the bus in a specific cycle. On global miss
cycles the device with LRAM = 1 (the default driv-
ing device for the SRAM bus) and LDEV = 1 (the
default driving device for SSF and SSV signals)
will be the default driver for such missed cycles.
Note:
During 144-bit searches of 144-bit-config-
ured tables, the search hit will always be at an
even address.
The SEARCH command is a pipelined operation.
It executes a search at half the rate of the frequen-
cy of CLK2X for 144-bit searches in x144-config-
ured tables. The latency of SADR, CE_L, ALE_L,
WE_L, SSV, and SSF from the 144-bit SEARCH
command cycle (two CLK2X cycles) is shown in
Table 40, page 90.
The latency of a search from command to the
SRAM access cycle is 6 for 1
–
31 devices in the ta-
ble and where TLSZ = 10. In addition, SSV and
SSF shift further to the right for different values of
HLAT, as specified in Table 41, page 90.
The 144-bit SEARCH operation is pipelined and
executes as follows:
–
Four cycles from the SEARCH command, each
of the devices knows the outcome internal to it
for that operation.
–
In the fifth cycle after the SEARCH command,
the devices in a block (being less than or equal
to eight devices resolving the winner within
them using the LHI[6:0] and LHO[1:0] signalling
mechanism) arbitrate for a winner amongst
them.
–
In the sixth cycle after the SEARCH command,
the blocks (of devices) resolve the winning block
through the BHI[2:0] and BHO[2:0] signalling
mechanism. The winning device in the winning
block is the global winning device for a
SEARCH operation.
Table 39. Hit/Miss Assumption
Search Number
1
2
3
4
Block 0
Miss
Miss
Miss
Miss
Block 1
Miss
Miss
Hit
Miss
Block 2
Miss
Hit
Hit
Miss
Block 3
Hit
Hit
Miss
Miss
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7040N-100ZA1T | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M708 | PCM REMOTE CONTROL TRANSMITTER |
| M708A | PCM REMOTE CONTROL TRANSMITTER |
| M708B1 | PCM REMOTE CONTROL TRANSMITTER |
| M708AB1 | PCM REMOTE CONTROL TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7040N-100ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M7041 | 制造商:Tamura Corporation of America 功能描述: |
| M7045 | 制造商:Tamura Corporation of America 功能描述: |
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| M705-5090242 | 功能描述:RCA Phono連接器 FEMALE STEREO JACK RoHS:否 制造商:Neutrik 型式:Male 端接類型:Solder 安裝風(fēng)格:Cable 方向:Horizontal |
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