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參數(shù)資料
| 型號(hào)： | M7040N-083ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 5600PF 100V 10% X7R AXIAL BULK P-MIL-PRF-39014 |
| 中文描述： | 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎 |
| 文件頁(yè)數(shù)： | 68/159頁(yè) |
| 文件大小： | 1088K |
| 代理商： | M7040N-083ZA1T |
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M7040N
68/159
144-bit Search on Tables Configured as x144 Using Up to Eight M7040N Devices
The hardware diagram of the search subsystem of
eight devices is shown in Figure 47, page 69. The
following are parameters programmed into the
eight devices:
–
First seven devices (devices 0
–
6):
CFG = 0101010101010101, TLSZ = 01,
HLAT = 010, LRAM = 0, and LDEV = 0.
–
Eighth device (device 7):
CFG = 0101010101010101, TLSZ = 01,
HLAT = 010, LRAM = 1, and LDEV = 1.
Note:
All eight devices must be programmed with
the same value of TLSZ and HLAT. Only the last
device in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 7 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
6 in this case).
Figure 49, page 71 shows the timing diagram for a
SEARCH command in the 144-bit-configured ta-
ble of eight devices for Device 0. Figure 50, page
72 shows the timing diagram for a SEARCH com-
mand in the 144-bit-configured table consisting of
eight devices for Device 1. Figure 51, page 73
shows the timing diagram for a SEARCH com-
mand in the 144-bit configured table consisting of
eight devices for Device 7 (the last device in this
specific table). For these timing diagrams, four
144-bit searches are performed sequentially, and
the following HIT/MISS assumptions were made
(see Table 36)
The following is the sequence of operation for a
single 144-bit SEARCH command (see COM-
MAND CODES AND PARAMETERS, page 30).
–
Cycle A:
The host ASIC drives CMDV high and
applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
for use in this SEARCH operation. CMD[8:6]
signals must be driven with the same bits that
will be driven by this device on SADR[23:21] if it
has a hit. DQ[71:0] must be driven with the 72-
bit data ([143:72]) in order to be compared
against all even locations. The CMD[2] signal
must be driven to a logic '0.'
–
Cycle B:
The host ASIC continues to drive
CMDV high and to apply the command code for
SEARCH
command
('10')
on
CMD[1:0].
CMD[5:2] must be driven by the index of the
comparand register pair for storing the 144-bit
word presented on the DQ Bus during Cycles A
and B. CMD[8:6] signals must be driven with the
SSR Index that will be used for storing the ad-
dress of the matching entry and the Hit Flag
(see
SEARCH-Successful
(SSR[0:7]), page 24). The DQ[71:0] is driven
with 72-bit data ([71:0]) compared against all
odd locations.
The logical 144-bit search operation is shown in
Figure 48, page 70. The entire table (eight devices
of 144-bit entries) is compared to a 144-bit word K
(presented on the DQ Bus in Cycles A and B of the
command) using the GMR and local mask bits.
The GMR is the 144-bit word specified by the even
and odd global mask pair selected by the GMR In-
dex in the command
’
s Cycle A.
The 144-bit word K (presented on the DQ Bus in
Cycles A and B of the command) is also stored in
the even and odd comparand registers specified
by the Comparand Register Index in the com-
mand
’
s Cycle B. In x144 configurations, the even
and odd comparand registers can subsequently
be used by the LEARN command in only one of
the devices (the first non-full device). The word K
(presented on the DQ Bus in Cycles A and B of the
command) is compared to each entry in the table
starting at location
“
0.
”
The first matching entry
’
s
location,
“
L,
”
is the winning address that is driven
as part of the SRAM address on the SADR[23:0]
lines (see SRAM ADDRESSING, page 128). The
global winning device will drive the bus in a specif-
ic cycle. On global miss cycles the device with
LRAM = 1 (the default driving device for the SRAM
Bus) and LDEV = 1 (the default driving device for
SSF and SSV signals) will be the default driver for
such missed cycles.
Note:
During 144-bit searches of 144-bit-config-
ured tables, the search hit will always be at an
even address.
The SEARCH command is a pipelined operation
and executes a search at half the rate of the fre-
quency of CLK2X for 144-bit searches in x144-
configured tables. The latency of SADR, CE_L,
ALE_L, WE_L, SSV, and SSF from the 144-bit
SEARCH command cycle (two CLK2X cycles) is
shown in Table 37, page 74.
For one to eight devices in the table and
TLSZ = 01, the latency of a SEARCH from com-
mand to SRAM access cycle is 5. In addition, SSV
and SSF shift further to the right for different val-
ues of HLAT as specified in Table 38, page 74.
Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7040N-100ZA1T | 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M708 | PCM REMOTE CONTROL TRANSMITTER |
| M708A | PCM REMOTE CONTROL TRANSMITTER |
| M708B1 | PCM REMOTE CONTROL TRANSMITTER |
| M708AB1 | PCM REMOTE CONTROL TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7040N-100ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE |
| M7041 | 制造商:Tamura Corporation of America 功能描述: |
| M7045 | 制造商:Tamura Corporation of America 功能描述: |
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