- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377840 > M95160-R (意法半導(dǎo)體) 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock PDF資料下載
參數(shù)資料
| 型號： | M95160-R |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| 中文描述： | 16千位和8千位串行SPI高速時鐘總線的EEPROM |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 270K |
| 代理商： | M95160-R |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
Connecting to the SPI bus
M95160, M95080
10/45
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4.
shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 4.
Bus master and memory devices on the SPI bus
1.
Figure 4
shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data Output (Q) line at a time, the other memory devices are high impedance.
The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
The pull-up resistor R (represented in
Figure 4
) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low
(while the S line is pulled High): this ensures that S and C do not become High at the same
time, and so, that the t
SHCH
requirement is met. The typical value of R is 100 k
.
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
C
Q
D
S
SPI Memory
Device
C
Q
D
S
SPI Memory
Device
C
Q
D
S
CS3
CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
R
R
R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95160-W | 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95128-MN6TPV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3GP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3GV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3PP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95160-R_12 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16-Kbit serial SPI bus EEPROM with high-speed clock |
| M95160-RBN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN3T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。