參數(shù)資料
型號(hào): M95160-R
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
中文描述: 16千位和8千位串行SPI高速時(shí)鐘總線的EEPROM
文件頁數(shù): 17/45頁
文件大?。?/td> 270K
代理商: M95160-R
M95160, M95080
Instructions
17/45
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
Figure 8.
, to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
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