- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377840 > M95160-R (意法半導(dǎo)體) 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock PDF資料下載
參數(shù)資料
| 型號： | M95160-R |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| 中文描述： | 16千位和8千位串行SPI高速時鐘總線的EEPROM |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 270K |
| 代理商： | M95160-R |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
Operating features
M95160, M95080
14/45
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
●
●
●
●
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
●
●
Table 3.
Write-Protected block size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95160
M95080
0
0
none
none
none
0
1
Upper quarter
0600h - 07FFh
0300h - 03FFh
1
0
Upper half
0400h - 07FFh
0200h - 03FFh
1
1
Whole memory
0000h - 07FFh
0000h - 03FFh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M95160-W | 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95128-MN6TPV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3GP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3GV | 128 Kbit Serial SPI bus EEPROM with high speed clock |
| M95128-DW3PP | 128 Kbit Serial SPI bus EEPROM with high speed clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95160-R_12 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16-Kbit serial SPI bus EEPROM with high-speed clock |
| M95160-RBN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN3T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。